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ds07-16312-1e fujitsu semiconductor data sheet 32-bit proprietary microcontrollers cmos fr30 family mb91151a series mb91151a n description the mb91151a is a single-chip microcontroller using a 32-bit risc-cpu (fr30 family) as its core. n features cpu ? 32-bit risc (fr30) , load/store architecture, 5-stage pipeline ? general-purpose registers : 32 bits 16 ? 16-bit fixed-length instructions (basic instructions) , 1 instruction/ 1 cycle ? memory-to-memory transfer, bit processing, barrel shift processing : optimized for embedded applications ? function entrance/exit instructions, and multiple load/store instructions of register contents, instruction systems supporting high level languages ? register interlock functions, efficient assembly language description ? branch instructions with delay slots : reduced overhead time in branching executions ? internal multiplier/supported at instruction level signed 32-bit multiplication : 5 cycles signed 16-bit multiplication : 3 cycles ? interrupt (pc and ps saving) : 6 cycles, 16 priority levels (continued) n pac k ag e 144-pin plastic lqfp (fpt-144p-m08)
mb91151a 2 (continued) bus interface ? 16-bit address output, 8/16-bit data input and output ? basic bus cycle : 2-clock cycle ? support for interface for various types of memory ? unused data/address pins can be configured as input/output ports ? support for little endian mode internal ram instruction ram : 2 kbytes data ram : 32 kbytes dmac dmac in descriptor format for placing transfer parameters on to the main memory. capable of transferring a maximum of eight internal and external factors combined. three channels for external factors bit search module searches in one cycle for the position of the bit that changes from the msb in one word to the initial 1/0. timers ? 16-bit ocu 8 channels, icu 4 channels, free-run timer 1 channel ? 8/16-bit up/down timer/counter (8-bit 2 channels or 16-bit 1 channel) ? 16-bit ppg timer 6 channels. the output pulse cycle and duty can be varied as desired. ? 16-bit reload timer 4 channels d/a converter ?8-bit 3 channels a/d converter (sequential comparison type) ?10-bit 8 channels ? sequential conversion method (conversion time : 5.0 m s@33 mhz) ? single conversion or scan conversion can be selected, and one-shot or continuous or stop conversion mode can be set respectively. ? conversion starting function by hardware/software. serial i/o ?uart 4 channels. any of them is capable of serial transfer in sync with clock attached with the lsb/msb switching function. ? serial data output and serial clock output are selectable by push-pull/open drain software. ? a 16-bit timer (u-timer) is contained as a dedicated baud rate generator allowing any baud rate to be generated. clock switching function ? gear function : operating clock ratios to the basic clock can be set independently for the cpu and peripherals from four types, 1 : 1, 1 : 2, 1 : 4 or 1 : 8. interrupt controller external interrupt input (16 channels in total) ? allows the rising edge/falling edge/h level/l level to be set. internal interrupt factors ? interrupt by resources and delay interrupt others ? reset cause : power on reset/watchdog timer/software reset/external reset ? low power consumption mode : sleep/stop ? package : 144-pin lqfp ? cmos technology (0.35 m m) ? power supply voltage : 3.15 v to 3.6 v
mb91151a 3 n pin assignment (top view) (fpt-144p-m08) p20/d16 p21/d17 p22/d18 p23/d19 p24/d20 p25/d21 p26/d22 p27/d23 v ss p30/d24 p31/d25 p32/d26 p33/d27 p34/d28 p35/d29 p36/d30 p37/d31 p40/a00 p41/a01 p42/a02 p43/a03 p44/a04 p45/a05 p46/a06 p47/a07 v ss v cc p50/a08 p51/a09 p52/a10 p53/a11 p54/a12 p55/a13 p56/a14 p57/a15 p60/a16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 p61/a17 p62/a18 p63/a19 p64/a20 p65/a21 p66/a22 p67/a23 v ss p80/rdy p81/bgrnt p82/brq p83/rd p84/wr0 p85/wr1 p86/clk md2 md1 md0 rst v cc x1 x0 v ss pc0/int0 pc1/int1 pc2/int2 pc3/int3 pc4/int4/cs0 pc5/int5/cs1 pc6/int6/cs2 pc7/int7/cs3 v cc pd0/ain0/int8/trg0 pd1/bin0/int9/trg1 pd2/ain1/int10/trg2 pd3/bin1/int11/trg3 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 ph5/sck1/to1 pi0/sin2 pi1/sot2 pi2/sck2/to2 pi3/sin3 pi4/sot3 pi5/sck3/to3 v ss pj0 pj1 v ss v cc pg5/ppg5 pg4/ppg4 pg3/ppg3 pg2/ppg2 pg1/ppg1 pg0/ppg0 pf4 pf3/in3 pf2/in2 pf1/in1 pf0/in0 pe7/oc7 pe6/oc6 pe5/oc5 pe4/oc4 pe3/oc3 pe2/oc2 pe1/oc1 pe0/oc0 v cc pd7/atg/int15 pd6/deop2/int14 pd5/zin1/int13/trg5 pd4/zin0/int12/trg4 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 v ss open open open v cc pk7/an7 pk6/an6 pk5/an5 pk4/an4 pk3/an3 pk2/an2 pk1/an1 pk0/an0 av ss avrl avrh av cc davc davs da0 da1 da2 v cc pl7/dack2 pl6/dreq2 pl5/deop1 pl4/dack1 pl3/dreq1 pl2/deop0 pl1/dack0 pl0/dreq0 ph0/sin0 ph1/sot0 ph2/sck0/to0 ph3/sin1 ph4/sot1
mb91151a 4 n pin description (continued) pin no. pin name circuit type function 1 2 3 4 5 6 7 8 d16/p20 d17/p21 d18/p22 d19/p23 d20/p24 d21/p25 d22/p26 d23/p27 c bit 16 to bit 23 of external data bus these pins are activated only in 16-bit external bus mode. these pins are available as ports in single-chip and 8-bit external bus modes. 10 11 12 13 14 15 16 17 d24/p30 d25/p31 d26/p32 d27/p33 d28p34 d29/p35 d30/p36 d31/p37 c bit 24 to bit 31 of external data bus these pins are available as ports in single-chip mode. 18 19 20 21 22 23 24 25 28 29 30 31 32 33 34 35 a00/p40 a01/p41 a02/p42 a03/p43 a04/p44 a05/p45 a06/p46 a07/p47 a08/p50 a09/p51 a10/p52 a11/p53 a12/p54 a13/p55 a14/p56 a15/p57 f bit 0 to bit 15 of external address bus these pins are activated in external bus mode. these pins are available as ports in single-chip mode. 36 37 38 39 40 41 42 43 a16/p60 a17/p61 a18/p62 a19/p63 a20/p64 a21/p65 a22/p66 a23/p67 o bit 16 to bit 23 of external address bus these pins are available as ports when the address bus is not in use. 45 rdy/p80 c external rdy input this function is activated when external rdy input is allowed. input 0 when the bus cycle being executed does not end. this pin is available as a port when external rdy input is not in use.
mb91151a 5 (continued) pin no. pin name circuit type function 46 bgrnt /p81 f external bus release acceptance output this function is activated when external bus release acceptance output is allowed. output l upon releasing of the external bus. this pin is available as a port when external bus release acceptance out- put is not allowed. 47 brq/p82 c external bus release request input this function is activated when external bus release request input is al- lowed. input 1 when the release of the external bus is desired. this pin is available as a port when external bus release request input is not in use. 48 rd /p83 f external bus read strobe output this function is activated when external bus read strobe output is allowed. this pin is available as a port when external bus read strobe output is not allowed. 49 wr0 /p84 f external bus write strobe output this function is activated in external bus mode. this pin is available as a port in single chip mode. 50 wr1 /p85 f external bus write strobe output this function is activated in external bus mode when the bus width is 16 bits. this pin is available as a port in single chip mode or when the external bus width is 8 bits. 51 clk/p86 f system clock output the pin outputs the same clock as the external bus operating frequency. the pin is available as a port when it is not used to output the clock. 52 53 54 md2 md1 md0 g mode pins to use these pins, connect them directly to either v cc or v ss . use these pins to set the basic mcu operating mode. 55 rst b external reset input 57 58 x1 x0 a high-speed clock oscillation pins 60 61 62 63 int0/pc0 int1/pc1 int2/pc2 int3/pc3 h external interrupt request input 0-3 since this input is used more or less continuously when the corresponding external interrupt is allowed, output by the port needs to be stopped ex- cept when it is performed deliberately. since this port is allowed to input also in standby mode, it can be used to reset the standby state. these pins are available as ports when external interrupt request input is not in use.
mb91151a 6 (continued) pin no. pin name circuit type function 64 65 66 67 int4/pc4/cs0 int5/pc5/cs1 int6/pc6/cs2 int7/pc7/cs3 h these pins also serve as the chip select output and external inter- rupt request input 4 to 7. when the chip select output is not allowed, these pins are available as external interrupt requests or ports. since this input is used more or less continuously when the corre- sponding external interrupt is allowed, output by the port needs to be stopped except when it is performed deliberately. since this port is also allowed to input in standby mode, the port can be used to reset the standby state. these pins are available as ports when external interrupt request input and chip select output are not in use. 69 70 71 72 73 74 pd0/ain0/int8/trg0 pd1/bin0/int9/trg1 pd2/ain1/int10/trg2 pd3/bin1/int11/trg3 pd4/zin0/int12/trg4 pd5/zin1/int13/trg5 h external interrupt request input 8 to 13 since this input is used more or less continuously when the corre- sponding external interrupt is allowed, output by the port needs to be stopped except when it is performed deliberately. [ain, bin] up/down timer input. [trg] ppg external trigger input. since this input is used more or less continuously while input is al- lowed, output by the port needs to be stopped except when it is per- formed deliberately. these pins are available as ports when the external interrupt re- quest input, up timer counter input, and ppg external trigger input are not in use. 75 pd6/deop2/int14 h external interrupt request input 14 since this input is used more or less continuously when the corre- sponding external interrupt is allowed, output by the port needs to be stopped except when it is performed deliberately. [deop2] dma external transfer end output. this function is activated when dmac external transfer end output is allowed. this pin is available as a port when it is not in use as the external interrupt request input or dma external transfer end output. 76 pd7/atg /int15 h external interrupt request input 15 since this input is used more or less continuously when the corre- sponding external interrupt is allowed, output by the port needs to be stopped except when it is performed deliberately. [atg ] a/d converter external trigger input. since this input is used more or less continuously when selected as an a/d activation factor, output by the port needs to be stopped ex- cept when it is performed deliberately. this pin is available as a port when it is not in use as the external interrupt request input or a/d converter external trigger input.
mb91151a 7 (continued) pin no. pin name circuit type function 78 79 80 81 82 83 84 85 pe0/oc0 pe1/oc1 pe2/oc2 pe3/oc3 pe4/oc4 pe5/oc5 pe6/oc6 pe7/oc7 f output compare output these pins are available as ports when output compare output is not al- lowed. 86 87 88 89 pf0/in0 pf1/in1 pf2/in2 pf3/in3 f input capture input this function is activated when the input capture operation is input. these pins are available as ports when input capture input is not in use. 90 pf4 f general i/o port 91 92 93 94 95 96 pg0/ppg0 pg1/ppg1 pg2/ppg2 pg3/ppg3 pg4/ppg4 pg5/ppg5 f ppg timer output this function is activated when ppg timer output is allowed. these pins are available as ports when ppg timer output is not allowed. 99 100 pj1 pj0 q general i/o port 102 pi5/sck3/to3 p uart3 clock i/o, reload timer 3 output when uart3 clock output is not allowed, reload timer 3 can be output by allowing it. this pin is available as a port when neither uart3 clock output nor reload timer output is allowed. 103 pi4/sot3 p uart3 data output this function is activated when uart3 data output is allowed. this pin is available as a port when uart3 clock output is not allowed. 104 pi3/sin3 p uart3 data input since this input is used more or less continuously while uart3 is en- gaged in input operations, output by the port needs to be stopped except when it is performed deliberately. this pin is available as a port when uart3 output data input is not in use.
mb91151a 8 (continued) pin no. pin name circuit type function 105 pi2/sck2/to2 p uart2 clock i/o, reload timer 2 output when uart2 clock output is not allowed, reload timer 2 can be output by allowing it. this pin is available as a port when neither uart2 clock output nor reload timer output is allowed. 106 pi1/sot2 p uart2 data output this function is activated when uart2 data output is allowed. this pin is available as a port when uart2 clock output is not allowed. 107 pi0/sin2 p uart2 data input since this input is used more or less continuously while uart2 is en- gaged in input operations, output by the port needs to be stopped except when it is performed deliberately. this pin is available as a port when uart2 data input is not in use. 108 ph5/sck1/to1 p uart1 clock i/o, reload timer 1 output when uart1 clock output is not allowed, reload timer 1 can be output by allowing it. this pin is available as a port when neither uart1 clock output nor reload timer output is allowed. 109 ph4/sot1 p uart1 data output this function is activated when uart1 data output is allowed. this pin is available as a port when uart1 clock output is not allowed. 110 ph3/sin1 p uart1 data input since this input is used more or less continuously while uart1 is en- gaged in input operations, output by the port needs to be stopped except when it is performed deliberately. this pin is available as a port when uart1 data input is not in use. 111 ph2/sck0/to0 p uart0 clock i/o, reload timer 0 output when uart0 clock output is not allowed, reload timer 0 can be output by allowing it. this pin is available as a port when neither uart0 clock output nor reload timer output is allowed. 112 ph1/sot0 p uart0 data output this function is activated when uart0 data output is allowed. this pin is available as a port when uart0 clock output is not allowed. 113 ph0/sin0 p uart0 data input since this input is used more or less continuously while uart0 is en- gaged in input operations, output by the port needs to be stopped except when it is performed deliberately. this pin is available as a port when uart0 data input is not in use. 114 dreq0/pl0 f dma external transfer request input since this input is used more or less continuously when selected as a dmac transfer factor, output by the port needs to be stopped except when it is performed deliberately. this pin is available as a port when dma external transfer request input is not in use.
mb91151a 9 (continued) pin no. pin name circuit type function 115 dack0/pl1 f dma external transfer request acceptance output this function is activated when the dmac external transfer request ac- ceptance is allowed to be output. this pin is available as a port when the dmac transfer request accep- tance is not allowed to be output. 116 deop0/pl2 f dma external transfer end output this function is activated when the end of dmac external transfer is al- lowed to be output. 117 dreq1/pl3 f dma external transfer request input since this input is used more or less continuously when selected as a dmac transfer factor, output by the port needs to be stopped except when it is performed deliberately. this pin is available as a port when dma external transfer request input is not in use. 118 dack1/pl4 f dma external transfer request acceptance output this function is activated when the dmac external transfer request ac- ceptance is allowed to be output. this pin is available as a port when dmac transfer request acceptance output is not allowed. 119 deop1/pl5 f dma external transfer end output this function is activated when the end of dmac external transfer is al- lowed to be output. 120 dreq2/pl6 f dma external transfer request input since this input is used more or less continuously when selected as a dmac transfer factor, output by the port needs to be stopped except when it is performed deliberately. this pin is available as a port when dma external transfer request input is not in use. 121 dack2/pl7 f dma external transfer request acceptance output this function is activated when the dmac external transfer request ac- ceptance is allowed to be output. this pin is available as a port when dmac transfer request acceptance output is not allowed. 123 124 125 da2 da1 da0 ? d/a converter output this function is activated when d/a converter output is allowed. 126 davs ? power supply pin for the d/a converter 127 davc ? power supply pin for the d/a converter 128 av cc ? vcc power supply for the a/d converter 129 avrh ? a/d converter reference voltage (high potential side) be sure to turn on/off this pin with potential higher than avrh applied to v cc . 130 avrl ? a/d converter reference voltage (low potential side) 131 av ss ? v ss power supply for the a/d converter
mb91151a 10 (continued) note : on the majority of pins listed above, the i/o port and the resource i/o are multiplexed, such as xxxx/pxx. when the port and the resource output compete against each other on these pins, priority is given to the resource. pin no. pin name circuit type function 132 133 134 135 136 137 138 139 an0/pk0 an1/pk1 an2/pk2 an3/pk3 an4/pk4 an5/pk5 an6/pk6 an7/pk7 n a/d converter analog input these pins are activated when the aic register is designated for ana- log input. these pins are available as ports when a/d converter analog input is not in use. 27, 56, 68, 77, 97, 122, 140 v cc ? power supply pin (v cc ) for digital circuit always power supply pin (v cc ) must be connected to the power supply. 9, 26, 44, 59, 98, 101, 144 v ss ? earth level (v ss ) for digital circuit always power supply pin (v ss ) must be connected to the power supply.
mb91151a 11 n i/o circuit type (continued) type circuit remarks a ? high-speed oscillation circuit oscillation feedback resistor = approx. 1 m w b ? cmos hysteresis input pin cmos hysteresis input (standby control not attached) pull-up resistor c ? cmos level i/o pin cmos level output cmos level input (attached with standby control) i ol = 4 ma f ? cmos hysteresis i/o pin cmos level output cmos hysteresis input (attached with standby control) i ol = 4 ma x1 x0 xout standby control signal digital input pout nout cmos input standby control r pout nout hysteresis input standby control r
mb91151a 12 (continued) type circuit remarks g ? cmos level input pin cmos level input (standby control not attached) h ? cmos hysteresis i/o pin with pull-up control cmos level output cmos level input (standby control not attached) pull-up resistance = approx. 50 k w (typ) i ol = 4 ma n ? analog/cmos level i/o pin. cmos level output cmos level input (attached with standby control) analog input (analog input is en- abled when aics corresponding bit is set to 1.) i ol = 4 ma r digital input r r pout pull-up control hysteresis input nout pout nout cmos input standby control analog input r
mb91151a 13 (continued) type circuit remarks o ? cmos hysteresis i/o pin with pull-up control cmos level output cmos hysteresis input (attached with standby control) pull-up resistance = approx. 50 k w (typ) i ol = 4 ma p ? cmos hysteresis i/o pin with pull-up control. cmos level output (attached with open drain con- trol) cmos hysteresis input (attached with standby control) pull-up resistance = approx. 50 k w (typ) i ol = 4 ma q ? open drain i/o pin ? 5 v tolerance of voltage ? cmos hysteresis input (attached with standby control) i ol = 15 ma pout pull-up control hysteresis input standby control nout r r nout pull-up control open drain control hysteresis input standby control r r nout hysteresis input standby control r
mb91151a 14 n handling devices 1. preventing latchup in cmos ics, applying voltage higher than v cc or lower than v ss to input/output pin or applying voltage over rating across v cc and v ss may cause latchup. this phenomenon rapidly increases the power supply current, which may result in thermal breakdown of the device. make sure to prevent the voltage from exceeding the maximum rating. 2. treatment of pins ? treatment of unused pins unused pins left open may cause malfunctions. make sure to connect them to pull-up or pull-down resistors. ? treatment of open pins be sure to use open pins in open state. ? treatment of output pins shortcircuiting an output pin with the power supply or with another output pin or connecting a large-capacity load may causes a flow of large current. if this conditions continues for a lengthy period of time, the device deteriorates. take great care not to exceed the absolute maximum ratings. ? mode pins ( md0 - md2 ) these pins should be used directly connected to either v cc or v ss . in order to prevent noise from causing accidental entry into test mode, keep the pattern length as short as possible between each mode pin and v cc or v ss on the board and connect them with low impedance. ? power supply pins when there are several v cc and v ss pins, each of them is equipotentially connected to its counterpart inside of the device, minimizing the risk of malfunctions such as latch up. to further reduce the risk of malfunctions, to prevent emi radiation, to prevent strobe signal malfunction resulting from creeping-up of ground level and to observe the total output current standard, connect all v cc and v ss pins to the power supply or gnd. it is preferred to connect v cc and v ss of mb91151a to power supply with minimal impedance possible. it is also recommended to connect a ceramic capacitor as a bypass capacitor of about 0.1 m f between v cc and v ss at a position as close as possible to mb91151a. ? crystal oscillator circuit noises around x0 and x1 pins may cause malfunctions of mb91151a. in designing the pc board, layout x0 and x1 and crystal oscillator (or ceramic oscillator) and bypass capacitor for grounding as close as possible. it is strongly recommended to design pc board so that x0, x1 pins are surrounded by grounding area for stable operation 3. precautions ? external reset input it takes at least 5 machine cycle to input l level to the rst pin and to ensure inner reset operation properly. ? external clocks when using an external clock, normally, a clock of which the phase is opposite to that of x0 must be supplied to the x0 and x1 pins simultaneously. however, when using the clock along with stop (oscillation stopped) mode, the x1 pin stops when h is input in stop mode. to prevent one output from competing against another, an external resistor of about 1 k w should be provided. the following figure shows an example usage of an external clock. an example usage of an external clock x0 x1 mb91151a
mb91151a 15 4. caution during powering up ? when powering up when turning on the power supply, never fail to start from setting the rst pin to l level. and after the power supply voltage goes to v cc level, at least after ensuring the time for 5 machine cycles, then set to h level. ? source oscillation input at turning on the power supply, never fail to input the clock before cancellation of the oscillation stabilizing waiting. ? power on resetting when powering up or when turning the power back on after the supply voltage drops below the operation assurance range, be sure to reset the power. ? power on sequence turn on the power in the order of v cc , av cc and avrh. the power should be disconnected in inverse order. ? even when an ad converter is not in use , connect av cc to the v cc level and av ss to the v ss level. ? even when a da converter is not in use , connect davc to the v cc level and davs to the v ss level.
mb91151a 16 n block diagram fr30 cpu core i - bus d - bus i - bus d - bus c - bus external bus ctl uart 4 ch utimer 4 ch 16 bit reload timer ram 2 kb clock control interrupt controller 8 bit up/down counter external interrupt 2 ch 4 ch 16 bit free run timer 1 ch 16 bit input capture 4 ch 16 bit output compare 10 bit 8 input a/d converter 8 bit 3 output d/a converter 8 ch 16 bit ppg 6 ch 16 ch instruction cache 1kb data ram dmac 8 ch bit search 32 kb d - bus r - bus p o r t d 8 ( ) p o r t l 8 ( ) p o r t 6 / 5 / 4 24 p o r t 3 / 2 16 m o d e 4 ( ) ( ) ( ) p o r t 8 7 ( ) p o r t c 8 ( ) pd7/int15/atg (i) pd6/int14/deop2 pd5/int13/zin1 pd4/int12/zin0 pd3/int11/bin1 pd2/int10/ain1 pd1/int9/bin0 (i) pd0/int8/ain0 (i) pc7/int7/cs3 pc6/int6/cs2 pc5/int5/cs1 pc4/int4/cs0 pc3/int3 pc2/int2 pc1/int1 pc0/int0 (i) a/d dmac up/down counter external interrupt osc (2) p o r t k 8 p o r t e 8 p o r t i 6 p o r t f 5 p o r t j 2 d a 3 ( ) ( ) ( ) p o r t h 6 ( ) p o r t g 6 ( ) ( ) ( ) ( ) pe7/oc7 pe6/oc6 pe5/oc5 pe4/oc4 pe3/oc3 pe2/oc2 pe1/oc1 pe0/oc0 pl7/dack2 pl6/dreq2 pl5/deop1 pl4/dack1 pl3/dreq1 pl2/deop0 (o) pl1/dack0 (o) pl0/dreq0 (i) p86/clk (o) p85/wr1 (o) p84/wr0 p83/rd (o) p82/brq (i) p81/bgrnt (o) p80/rdy (i) p67/a23 (o) p60/a16 p57/a15 p50/a08 p47/a07 p40/a00 p37/d31 (io) p30/d24 p27/d23 p20/d16 pg5/ppg5 pg4/ppg4 pg3/ppg3 pg2/ppg2 pg1/ppg1 pg0/ppg0 pf4 pf3/in3 pf2/in2 pf1/in1 pf0/in0 da2 da1 da0 x0 (i) x1 (i) ph0/sin0 ph1/sot0 ph2/sck0/to0 ph3/sin1 ph4/sot1 ph5/sck1/to1 pi0/sin2 pi1/sot2 pi2/sck2/to2 pi3/sin3 pi4/sot3 pi5/sck3/to3 pk0/an0 pk1/an1 pk2/an2 pk3/an3 pk4/an4 pk5/an5 pk6/an6 pk7/an7 pj0 pj1 uart tox: reload timer ppg input capture clock dmac bus control address data output compare a/d ~ ~ ~ ~ ~ ~ ~ ~ md1 md2 rst md0
mb91151a 17 n cpu core 1. memory space the fr family has a logical address space of 4 gbytes (2 32 bytes) and the cpu linearly accesses the memory space. ? direct addressing area the following area in the address space is used for i/o. this area is called direct addressing area and an operand address can be specified directly in an instruction. the direct addressing area varies with the data size to be accessed as follows : 2. memory map ? byte data access : 000 h -0ff h ? half word data access : 000 h -1ff h ? word data access : 000 h -3ff h 0000 0000 h 0000 0400 h 0000 0800 h 0000 1000 h 0000 9000 h 0001 0000 h ffff ffff h 0001 0000 h direct addressing area see " n i/o map" 0008 0000 h 0008 0800 h 0010 0000 h ffff ffff h i/o i/o i/o external bus mode serial start up mode i/o not accessible not accessible 32 kb internal ram 32 kb internal ram not accessible external area not accessible not accessible 2 kb internal ram serial rom 2kb not accessible not accessible 000f f800 h
mb91151a 18 3. registers the family of fr microcontrollers has two types of registers : the registers residing in the cpu which are dedicated to applications and the general-purpose registers residing in the memory. ? dedicated registers : ? program status (ps) the ps register holds program status and is further divided into three registers which are a condition code register (ccr) , a system condition code register (scr) , and an interrupt level mask register (ilm) . program counter (pc) : a 32-bit register to indicate the location where an instructions is stored. program status (ps) : a 32-bit register to store a register pointer or a condition code. tablebase register (tbr) : holds the vector table lead address used when eit (exceptions/interrupt/ trap) is processed. return pointer (rp) : holds the address to return from a subroutine. system stack pointer (ssp) : points to the system stack space. user stack pointer (usp) : points to the user stack space. multiplication and division result register (mdh/mdl) : a 32-bit multiplication and division register. pc ps tbr rp ssp usp mdh mdl program counter program status tablebase register return pointer system stack pointer user stack pointer multiplication and division register (undefined) (undefined) (undefined) (undefined) (undefined) xxxx xxxx h xxxx xxxx h xxxx xxxx h xxxx xxxx h xxxx xxxx h 0000 0000 h 000f fc00 h 32 bit initial value ps ilm4 ilm3 ilm2 ilm scr ccr ilm1 ilm0 d1 d0 t s i n z v c 0 1 2 3 4 5 6 7 8 9 10 16 17 18 19 20 31 ????
mb91151a 19 ? condition code register ( ccr ) ? system condition code register ( scr ) ? interrupt level mask register ( ilm ) s flag : designates the stack pointer for use as r15. i flag : controls enabling and disabling of user interrupt requests. n flag : indicates the sign when arithmetic operation results are considered to be an integer represented by 2s complement. z flag : indicates if arithmetic results were 0. v flag : considers the operand used for an arithmetic operation to be an integer represented by 2s com- plement and indicates if the operation resulted in an overflow. c flag : indicates whether or not an arithmetic operation resulted in a carry or a borrow from the most sig- nificant bit. t flag : designates whether or not to enable step trace trap. ilm4 to ilm0 : holds an interrupt level mask value to be used for level masking. an interrupt request is accepted only if the corresponding interrupt level among interrupt requests input to the cpu is higher than the value indicated by the ilm register. ilm4 ilm3 ilm2 ilm1 ilm0 interrupt level high-low 00000 0higher 0100015 1 1 1 1 1 31 lower
mb91151a 20 n instruction cache ? description the instruction cache is a temporary storage memory. in the event that the instruction codes are accessed from a low speed external memory, it holds the accessed codes internally, and is used to increase the access speed for all subsequent accesses. direct read or write access can not be done by instruction cache or instruction cache tag using software. ? instruction cache configuration basic instruction length of fr series : 2 bytes block layout : 2-way set associative type block 1 way is configured of 32 blocks. 1 block is 16 bytes ( = 4 sub blocks) 1 sub block is 4 bytes ( = 1 bus access unit) cash tag cash tag cash tag cash tag cash tag i3 4 bytes i2 4 bytes i1 4 bytes i0 4 bytes sub clock 0 sub clock 1 sub clock 2 sub clock 3 sub clock 0 sub clock 1 sub clock 2 sub clock 3 sub clock 0 sub clock 1 sub clock 2 sub clock 3 sub clock 0 sub clock 1 sub clock 2 sub clock 3 clock 0 clock 31 clock 31 clock 0 way 1 way 2 32 blocks 32 blocks ? instruction cache configuration
mb91151a 21 n general-purpose registers general-purpose registers are cpu registers r0 through r15 and used as accumulators during various oper- ations and as memory access pointers (fields indicating addresses) . of the 16 general-purpose registers, the following registers are assumed for specific applications. for this reason, some instructions are enhanced. r13 : virtual accumulator (ac) r14 : frame pointer (fp) r15 : stack pointer (sp) initial values to which r0 through r14 are reset are not defined. the initial value of r15 is 0000 0000 h (the ssp value) . ? register bank configuration r0 r1 r12 r13 r14 r15 ac (accumulator) fp (frame pointer) sp (stack pointer) xxxx xxxx h initial value xxxx xxxx h 0000 0000 h 32 bits
mb91151a 22 n mode setting 1. mode pins as shown below, three pins, md2, md1, and md0 are used to indicate an operation. mode pins and set modes * : not available on this product type 2. mode data the data which the cpu writes to 0000 07ff h after reset is called mode data. it is the mode register (modr) that exists at 0000 07ff h . once a mode is set in this register, operations will take place in that mode. the mode register can be written only once after reset. the mode specified in the register is enabled immediately after it is written. [bits 7 and 6] : m1, m0 these are bus mode setting bits. specify the bus mode to be set to after writing to the mode register. note : of the above options, only 01 or 10 should be set for this model. [bits 5 to 0] : * these bits are reserved for the system. 0 should be written to these bits at all times. mode pin mode name reset vector access area external data bus width bus modes md2 md1 md0 0 0 0 external vector mode 0 external 8 bits external bus mode 0 0 1 external vector mode 1 external 16 bits 0 1 0 external vector mode 2 external 32 bits not available on this product type 0 1 1 external vector mode internal (mode register) single-chip mode* 1 ?? ? ? ? not available m1 m0 function remarks 0 0 single-chip mode setting not allowed 0 1 internal ram-external bus mode 1 0 external bus mode 11 ? setting not allowed modr initial value access address : 0000 07ff h xxxxxxxx w w : write only, x : undefined m1 m0 bus mode setting bits ******
mb91151a 23 [precautions when writing to the modr] before writing to the modr, be sure to set amd0 through amd5 and determine the bus width in each cs (chip select) area. the modr does not have bus width setting bits. the bus width value set with mode pins md2 through md0 is enabled before writing to the modr and the bus width value set with bw1 and bw0 of amd0 through amd5 is enabled after writing to the modr. for example, the external reset vector is normally executed with area 0 (the area where cs0 is active) and the bus width at that time is determined by pins md2 through md0. suppose that the bus width is set to 32 or 16 bits in md2 though md0 but no value is specified in amd0. if the modr is written in this state, area 0 then switches to 8-bit bus mode and operates the bus since the initial bus width in amd0 is set to 8 bits. this causes a malfunction. in order to prevent this type of problem, amd0 through amd5 must always be set before writing to the modr. writing to the modr. amd0 to amd5 bw1, bw0 designated bus width : md2,md1,md0 rst (reset)
mb91151a 24 n i/o map (continued) address register block + + + + 0 + + + + 1 + + + + 2 + + + + 3 000000 h pdr3 (r/w) xxxxxxxx pdr2 (r/w) xxxxxxxx ? port data register 000004 h ? pdr6 (r/w) xxxxxxxx pdr5 (r/w) xxxxxxxx pdr4 (r/w) xxxxxxxx 000008 h ? pdr8 (r/w) - xxxxxxx 00000c h ? 000010 h pdrf (r/w) - - - xxxxx pdre (r/w) xxxxxxxx pdrd (r/w) xxxxxxxx pdrc (r/w) xxxxxxxx 000014 h pdrj (r/w) - - - - - - 11 pdri (r/w) - - xxxxxx pdrh (r/w) - - xxxxxx pdrg (r/w) - - xxxxxx 000018 h ? pdrl (r/w) xxxxxxxx pdrk (r/w) xxxxxxxx 00001c h ssr0 (r, r/w) 00001000 sidr0/sodr0 (r, w) xxxxxxxx scr0 (r/w, w) 00000100 smr0 (r/w) 00000 - 00 uart0 000020 h ssr1 (r, r/w) 00001000 sidr1/sodr1 (r, w) xxxxxxxx scr1 (r/w, w) 00000100 smr1 (r/w) 00000 - 00 uart1 000024 h ssr2 (r, r/w) 00001000 sidr2/sodr2 (r, w) xxxxxxxx scr2 (r/w, w) 00000100 smr2 (r/w) 00000 - 00 uart2 000028 h ssr3 (r, r/w) 00001000 sidr3/sodr3 (r, w) xxxxxxxx scr3 (r/w, w) 00000100 smr3 (r/w) 00000 - 00 uart3 00002c h tmrlr0 (w) xxxxxxxx xxxxxxxx tmr0 (r) xxxxxxxx xxxxxxxx reload timer 0 000030 h ? tmcsr0 (r/w) - - - - 0000 00000000 000034 h tmrlr1 (w) xxxxxxxx xxxxxxxx tmr1 (r) xxxxxxxx xxxxxxxx reload timer 1 000038 h ? tmcsr1 (r/w) - - - - 0000 00000000 00003c h tmrlr2 (w) xxxxxxxx xxxxxxxx tmr2 (r) xxxxxxxx xxxxxxxx reload timer 2 000040 h ? tmcsr2 (r/w) - - - - 0000 00000000
mb91151a 25 (continued) address register block + + + + 0 + + + + 1 + + + + 2 + + + + 3 000044 h tmrlr3 (w) xxxxxxxx xxxxxxxx tmr3 (r) xxxxxxxx xxxxxxxx reload timer 3 000048 h ? tmcsr3 (r/w) - - - - 0000 00000000 00004c h cdcr1 (r/w) 0 - - - 0000 ? cdcr0 (r/w) 0 - - - 0000 ? communications prescaler 1 000050 h cdcr3 (r/w) 0 - - - 0000 ? cdcr2 (r/w) 0 - - - 0000 ? 000054 h to 000058 h ? reserved 00005c h rcr1 (w) 00000000 rcr0 (w) 00000000 udcr1 (r) 00000000 udcr0 (r) 00000000 8/16 bit u/d counter 000060 h ccrh0 (r/w) 00000000 ccrl0 (r/w, w) - 000x000 ? csr0 (r/w, r) 00000000 000064 h ccrh1 (r/w) - 0000000 ccrl1 (r/w, w) - 000x000 ? csr1 (r/w, r) 00000000 000068 h ipcp1 (r) xxxxxxxx xxxxxxxx ipcp0 (r) xxxxxxxx xxxxxxxx 16 bit icu 00006c h ipcp3 (r) xxxxxxxx xxxxxxxx ipcp2 (r) xxxxxxxx xxxxxxxx 000070 h ? ics23 (r/w) 00000000 ? ics01 (r/w) 00000000 000074 h occp1 (r/w) xxxxxxxx xxxxxxxx occp0 (r/w) xxxxxxxx xxxxxxxx 16 bit ocu 000078 h occp3 (r/w) xxxxxxxx xxxxxxxx occp2 (r/w) xxxxxxxx xxxxxxxx 00007c h occp5 (r/w) xxxxxxxx xxxxxxxx occp4 (r/w) xxxxxxxx xxxxxxxx 000080 h occp7 (r/w) xxxxxxxx xxxxxxxx occp6 (r/w) xxxxxxxx xxxxxxxx 000084 h ocs2, 3 (r/w) xxx00000 0000xx00 ocs0, 1 (r/w) xxx00000 0000xx00 000088 h ocs6, 7 (r/w) xxx00000 0000xx00 ocs4, 5 (r/w) xxx00000 0000xx00 00008c h tcdt (r/w) 00000000 00000000 tccs (r/w) 0 - - - - - - - 00000000 16 bit freerun timer 000090 h stpr0 (r/w) 0000 - - - - stpr1 (r/w) 00000 - 00 stpr2 (r/w) 000000 - - ? stop register 0, 1, 2 000094 h gcn1 (r/w) 00110010 00010000 ? gcn2 (r/w) 00000000 ppg ctl
mb91151a 26 (continued) address register block + + + + 0 + + + + 1 + + + + 2 + + + + 3 000098 h ptmr0 (r) 11111111 11111111 pcsr0 (w) xxxxxxxx xxxxxxxx ppg0 00009c h pdut0 (w) xxxxxxxx xxxxxxxx pcnh0 (r/w) 0000000 - pcnl0 (r/w) 00000000 0000a0 h ptmr1 (r) 11111111 11111111 pcsr1 (w) xxxxxxxx xxxxxxxx ppg1 0000a4 h pdut1 (w) xxxxxxxx xxxxxxxx pcnh1 (r/w) 0000000 - pcnl1 (r/w) 00000000 0000a8 h ptmr2 (r) 11111111 11111111 pcsr2 (w) xxxxxxxx xxxxxxxx ppg2 0000ac h pdut2 (w) xxxxxxxx xxxxxxxx pcnh2 (r/w) 0000000 - pcnl2 (r/w) 00000000 0000b0 h ptmr3 (r) 11111111 11111111 pcsr3 (w) xxxxxxxx xxxxxxxx ppg3 0000b4 h pdut3 (w) xxxxxxxx xxxxxxxx pcnh3 (r/w) 0000000 - pcnl3 (r/w) 00000000 0000b8 h ptmr4 (r) 11111111 11111111 pcsr4 (w) xxxxxxxx xxxxxxxx ppg4 0000bc h pdut4 (w) xxxxxxxx xxxxxxxx pcnh4 (r/w) 0000000 - pcnl4 (r/w) 00000000 0000c0 h ptmr5 (r) 11111111 11111111 pcsr5 (w) xxxxxxxx xxxxxxxx ppg5 0000c4 h pdut5 (w) xxxxxxxx xxxxxxxx pcnh5 (r/w) 0000000 - pcnl5 (r/w) 00000000 0000c8 h eirr0 (r/w) 00000000 enir0 (r/w) 00000000 eirr1 (r/w) 00000000 enir1 (r/w) 00000000 ext int 0000cc h elvr0 (r/w) 00000000 00000000 elvr1 (r/w) 00000000 00000000 0000d0 h to 0000d8 h ? reserved 0000dc h ? dacr2 (r/w) - - - - - - - 0 dacr1 (r/w) - - - - - - - 0 dacr0 (r/w) - - - - - - - 0 d/a converter 0000e0 h ? dadr2 (r/w) xxxxxxxx dadr1 (r/w) xxxxxxxx dadr0 (r/w) xxxxxxxx 0000e4 h adcr (r, w) 00101- xx xxxxxxxx adcs1 (r/w, w) 00000000 adcs0 (r/w) 00000000 a/d converter (sequential type) 0000e8 h ? aick (r/w) 00000000 analog input control 0000ec h to 0000f0 h ? reserved
mb91151a 27 (continued) address register block + + + + 0 + + + + 1 + + + + 2 + + + + 3 0000f4 h pcri (r/w) - - 000000 pcrh (r/w) - - 000000 pcrd (r/w) 00000000 pcrc (r/w) 00000000 pull up control 0000f8 h ocri (r/w) - - 000000 ocrh (r/w) - - 000000 ? open drain control 0000fc h ddrf (r/w) - - - 00000 ddre (r/w) 00000000 ddrd (r/w) 00000000 ddrc (r/w) 00000000 data direction reg- ister 000100 h ? ddri (r/w) - 0000000 ddrh (r/w) - - 000000 ddrg (r/w) - - 000000 000104 h ? ddrl (r/w) 00000000 ddrk (r/w) 00000000 000108 h to 0001fc h ? reserved 000200 h dpdp (r/w) - - - - - - - - - - - - - - - - - - - - - - - - - 0000000 dmac 000204 h dacsr (r/w) 00000000 00000000 00000000 00000000 000208 h datcr (r/w) xxxxxxxx xxxx0000 xxxx0000 xxxx0000 00020c h to 0003e0 h ? reserved 0003e4 h ichcr (r/w) - - - - - - - - - - - - - - - - - - - - - - - - - - 000000 instruction cache 0003e8 h to 0003ec h ? reserved 0003f0 h bsd0 (w) xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx bit search module 0003e4 h bsd1 (r/w) xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0003f8 h bsdc (w) xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0003fc h bsrr (r) xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
mb91151a 28 (continued) address register block + + + + 0 + + + + 1 + + + + 2 + + + + 3 000400 h icr00 (r/w) - - - - 1111 icr01 (r/w) - - - - 1111 icr02 (r/w) - - - - 1111 icr03 (r/w) - - - - 1111 interrupt control unit 000404 h icr04 (r/w) - - - - 1111 icr05 (r/w) - - - - 1111 icr06 (r/w) - - - - 1111 icr07 (r/w) - - - - 1111 000408 h icr08 (r/w) - - - - 1111 icr09 (r/w) - - - - 1111 icr10 (r/w) - - - - 1111 icr11 (r/w) - - - - 1111 00040c h icr12 (r/w) - - - - 1111 icr13 (r/w) - - - - 1111 icr14 (r/w) - - - - 1111 icr15 (r/w) - - - - 1111 000410 h icr16 (r/w) - - - - 1111 icr17 (r/w) - - - - 1111 icr18 (r/w) - - - - 1111 icr19 (r/w) - - - - 1111 000414 h icr20 (r/w) - - - - 1111 icr21 (r/w) - - - - 1111 icr22 (r/w) - - - - 1111 icr23 (r/w) - - - - 1111 000418 h icr24 (r/w) - - - - 1111 icr25 (r/w) - - - - 1111 icr26 (r/w) - - - - 1111 icr27 (r/w) - - - - 1111 00041c h icr28 (r/w) - - - - 1111 icr29 (r/w) - - - - 1111 icr30 (r/w) - - - - 1111 icr31 (r/w) - - - - 1111 000420 h icr32 (r/w) - - - - 1111 icr33 (r/w) - - - - 1111 icr34 (r/w) - - - - 1111 icr35 (r/w) - - - - 1111 000424 h icr36 (r/w) - - - - 1111 icr37 (r/w) - - - - 1111 icr38 (r/w) - - - - 1111 icr39 (r/w) - - - - 1111 000428 h icr40 (r/w) - - - - 1111 icr41 (r/w) - - - - 1111 icr42 (r/w) - - - - 1111 icr43 (r/w) - - - - 1111 00042c h icr44 (r/w) - - - - 1111 icr45 (r/w) - - - - 1111 icr46 (r/w) - - - - 1111 icr47 (r/w) - - - - 1111 000430 h dicr (r/w) - - - - - - - 0 hrcl (r/w) - - - - 1111 ? delay int 000434 h to 00047c h ? reserved 000480 h rsrr/wtcr (r, w) 1-xxx-00 stcr (r/w, w) 000111- - pdrr (r/w) - - - - 0000 ctbr (w) xxxxxxxx clock control unit 000484 h gcr (r/w, r) 110011-1 wpr (w) xxxxxxxx ? 000488 h ptcr (r/w) 00xx0xxx ? pll control 00048c h to 0005fc h ? reserved
mb91151a 29 (continued) note : do not execute rmw instructions on registers having a write-only bit. rmw instructions (rmw : read modify write) data is undefined in reserved or ( ? ) areas. address register block + + + + 0 + + + + 1 + + + + 2 + + + + 3 000600 h ddr3 (w) 00000000 ddr2 (w) 00000000 ?? data direction register 000604 h ? ddr6 (w) 00000000 ddr5 (w) 00000000 ddr4 (w) 00000000 000608 h ? ddr8 (w) - 0000000 00060c h asr1 (w) 00000000 00000001 amr1 (w) 00000000 00000000 t-unit 000610 h asr2 (w) 00000000 00000010 amr2 (w) 00000000 00000000 000614 h asr3 (w) 00000000 00000011 amr3 (w) 00000000 00000000 000618 h asr4 (w) 00000000 00000100 amr4 (w) 00000000 00000000 00061c h asr5 (w) 00000000 00000101 amr5 (w) 00000000 00000000 000620 h amd0 (r/w) - - - 00111 amd1 (r/w) 0 - - 00000 amd32 (r/w) 00000000 amd4 (r/w) 0 - - 00000 000624 h amd5 (r/w) 0 - - 00000 ? 000628 h epcr0 (w) - - - - 1100 -1111111 epcr1 (w) - - - - - - - - 11111111 00062c h ? reserved 000630 h ? pcr6 (r/w) 00000000 ? pull up control 000634 h to 0007f8 h ? reserved 0007fc h ? ler (w) - - - - - 000 modr (w) xxxxxxxx little endian register mode register and rj, @ri or rj, @ri eor rj, @ri andh rj, @ri orh rj, @ri eorh rj, @ri andb rj, @ri orb rj, @ri eorb rj, @ri bandl #u4, @ri borl #u4, @ri beorl #u4, @ri bandh #u4, @ri borh #u4, @ri beorh #u4, @ri ( ) : access w : write only r/w : read/write enabled ? : not in use r : read only x : undefined
mb91151a 30 n interrupt factors and assignment of interrupt vectors and resisters (continued) factor interrupt no. interrupt level offset default tbr address decimal hex. reset 0 00 ? 3fc h 000ffffc h reserved for the system 1 01 ? 3f8 h 000ffff8 h reserved for the system 2 02 ? 3f4 h 000ffff4 h reserved for the system 3 03 ? 3f0 h 000ffff0 h reserved for the system 4 04 ? 3ec h 000fffec h reserved for the system 5 05 ? 3e8 h 000fffe8 h reserved for the system 6 06 ? 3e4 h 000fffe4 h reserved for the system 7 07 ? 3e0 h 000fffe0 h reserved for the system 8 08 ? 3dc h 000fffdc h reserved for the system 9 09 ? 3d8 h 000fffd8 h reserved for the system 10 0a ? 3d4 h 000fffd4 h reserved for the system 11 0b ? 3d0 h 000fffd0 h reserved for the system 12 0c ? 3cc h 000fffcc h reserved for the system 13 0d ? 3c8 h 000fffc8 h undefined instruction exception 14 0e ? 3c4 h 000fffc4 h reserved for the system 15 0f ? 3c0 h 000fffc0 h external interrupt 0 16 10 icr00 3bc h 000fffbc h external interrupt 1 17 11 icr01 3b8 h 000fffb8 h external interrupt 2 18 12 icr02 3b4 h 000fffb4 h external interrupt 3 19 13 icr03 3b0 h 000fffb0 h external interrupt 4 20 14 icr04 3ac h 000fffac h external interrupt 5 21 15 icr05 3a8 h 000fffa8 h external interrupt 6 22 16 icr06 3a4 h 000fffa4 h external interrupt 7 23 17 icr07 3a0 h 000fffa0 h external interrupts 8 to 15 24 18 icr08 39c h 000fff9c h reserved for the system 25 19 ? 398 h 000fff98 h uart0 (receiving complete) 26 1a icr10 394 h 000fff94 h uart1 (receiving complete) 27 1b icr11 390 h 000fff90 h uart2 (receiving complete) 28 1c icr12 38c h 000fff8c h uart3 (receiving complete) 29 1d icr13 388 h 000fff88 h reserved for the system 30 1e ? 384 h 000fff84 h uart0 (sending complete) 31 1f icr15 380 h 000fff80 h uart1 (sending complete) 32 20 icr16 37c h 000fff7c h uart2 (sending complete) 33 21 icr17 378 h 000fff78 h
mb91151a 31 (continued) factor interrupt no. interrupt level offset default tbr address decimal hex. uart3 (sending complete) 34 22 icr18 374 h 000fff74 h system reservation 35 23 ? 370 h 000fff70 h dmac (end, error) 36 24 icr20 36c h 000fff6c h reload timer 0 37 25 icr21 368 h 000fff68 h reload timer 1 38 26 icr22 364 h 000fff64 h reload timer 2 39 27 icr23 360 h 000fff60 h reload timer 3 40 28 icr24 35c h 000fff5c h a/d (sequential type) 42 2a icr26 354 h 000fff54 h ppg0 43 2b icr27 350 h 000fff50 h ppg1 44 2c icr28 34c h 000fff4c h ppg2 45 2d icr29 348 h 000fff48 h ppg3 46 2e icr30 344 h 000fff44 h ppg4 47 2f icr31 340 h 000fff40 h ppg5 48 30 icr32 33c h 000fff3c h u/dcounter 0 (compare/underflow, overflow, up-down inversion) 49 31 icr33 338 h 000fff38 h u/dcounter 1 (compare/underflow, overflow, up-down inversion 50 32 icr34 334 h 000fff34 h icu0 (read) 51 33 icr35 330 h 000fff30 h icu1 (read) 52 34 icr36 32c h 000fff2c h icu2 (read) 53 35 icr37 328 h 000fff28 h icu3 (read) 54 36 icr38 324 h 000fff24 h ocu0 (match) 55 37 icr39 320 h 000fff20 h ocu1 (match) 56 38 icr40 31c h 000fff1c h ocu2 (match) 57 39 icr41 318 h 000fff18 h ocu3 (match) 58 3a icr42 314 h 000fff14 h ocu4/5 (match) 59 3b icr43 310 h 000fff10 h ocu6/7 (match) 60 3c icr44 30c h 000fff0c h reserved for the system 61 3d ? 308 h 000fff08 h 16-bit free-run timer 62 3e icr46 304 h 000fff04 h delay interrupt factor bit 63 3f icr47 300 h 000fff00 h
mb91151a 32 (continued) * : realos/fr uses 0x40 and 0x41 interrupts for system codes. factor interrupt no. interrupt level offset default tbr address decimal hex. reserved for the system (used by realos*) 64 40 ? 2fc h 000ffefc h reserved for the system (used by realos*) 65 41 ? 2f8 h 000ffef8 h reserved for the system 66 42 ? 2f4 h 000ffef4 h reserved for the system 67 43 ? 2f0 h 000ffef0 h reserved for the system 68 44 ? 2ec h 000ffeec h reserved for the system 69 45 ? 2e8 h 000ffee8 h reserved for the system 70 46 ? 2e4 h 000ffee4 h reserved for the system 71 47 ? 2e0 h 000ffee0 h reserved for the system 72 48 ? 2dc h 000ffedc h reserved for the system 73 49 ? 2d8 h 000ffed8 h reserved for the system 74 4a ? 2d4 h 000ffed4 h reserved for the system 75 4b ? 2d0 h 000ffed0 h reserved for the system 76 4c ? 2cc h 000ffecc h reserved for the system 77 4d ? 2c8 h 000ffec8 h reserved for the system 78 4e ? 2c4 h 000ffec4 h reserved for the system 79 4f ? 2c0 h 000ffec0 h used with the int instruction 80 to 255 50 to ff ? 2bc h to 000 h 000ffebc h to 000ffc00 h
mb91151a 33 n peripheral resources 1. i/o port (1) port block diagram this lsi is available as an i/o port when the resource associated with each pin is set not to use a pin for input/ output. the pin level is read from the port (pdr) when it is set for input. when the port is set for output, the value in the data register is read. the same also applies to reload by read modify write. when switching from input to output, output data is set in the data register beforehand. however, if a read modify write instruction (such as bit set) is used at that time, keep in mind that it is the input data from the pin that is read, not the latch value of the data register. ? basic i / o port the i/o port consists of the pdr (port data register) and the ddr (data direction register) . notes : aic controls switching between the resource and port of the analog pin (a/d) . aick (analog input control register on port-k) the register controls whether port k should be used for analog input or as a general-purpose port. 0 : general-purpose port 1 : analog input (a/d) in input mode (ddr = 0) ? pdr read : reads the level of the corresponding external pin. pdr write : writes the set value to the pdr. in output mode (ddr = 1) ? pdr read : reads the pdr value. pdr write : outputs the pdr value to the corresponding external pin. data bus pdr read 0 1 0 1 pin pdr ddr pdr : port data register ddr : data direction register resource input resource output resource output allowed
mb91151a 34 ? i / o port ( attached with a pull - up resistor ) notes : pull-up resistor control register (pcr) r/w controls turning the pull-up resistor on/off. 0 : pull-up resistor disabled 1 : pull-up resistor enabled in stop mode priority is also given to the setting of the pull-up resistor control register. this function is not available when a relevant pin is in use as an external bus pin. do not write 1 to this register. data bus pdr read 0 1 0 1 pin pdr ddr pcr pdr : port data register ddr : data direction register pcr : pull-up control register resource output resource input resource output allowed pull-up resistor (approx. 50 k w )
mb91151a 35 ? i / o port ( attached with the open drain output function and a pull-up resistor ) notes : pull-up resistor setup register (pcr) r/w controls turning the pull-up resistor on/off. 0 : pull-up resistor disabled 1 : pull-up resistor enabled open drain control register (ocr) r/w controls open drain in output mode. 0 : standard output port during output mode 1 : open-drain output port during output mode this register has no significance in input mode (output high-z) . input/output mode is determined by the direction register (ddr) . priority is also given to the setting of the pull-up resistor control register in stop mode. when a relevant pin is used as an external bus pin, neither function is available. do not write 1 to either register. data bus pdr read 0 1 0 1 pin resource input resource output resource output allowed pdr ddr ocr pcr pdr ddr ocr pcr : port data register : data direction register : opendrain control register : pull-up control register
mb91151a 36 ? i / o port ( open drain ) notes : when using as an input port or for resource input, set the pdr and resource output to 1. during read by rmw, it is the pdr value that is read, not the pin value. data bus pdr read rmw = 0 rmw = 1 pin resource input resource output pdr rmw pdr : port data register
mb91151a 37 (2) register descriptions ? port data register ( pdr ) pdr2 to pdrl are the i/o data registers of the i/o port. input/output is controlled with corresponding ddr2 to ddrl. r/w : read/write enabled, x : undefined, ? : not in use pdr2 initial value access address : 000001 h xxxxxxxx b r/w pdr3 initial value access address : 000000 h xxxxxxxx b r/w pdr4 initial value access address : 000007 h xxxxxxxx b r/w pdr5 initial value access address : 000006 h xxxxxxxx b r/w pdr6 initial value access address : 000005 h xxxxxxxx b r/w pdr8 initial value access address : 00000b h - xxxxxxx b r/w pdrc initial value access address : 000013 h xxxxxxxx b r/w pdrd initial value access address : 000012 h xxxxxxxx b r/w pdre initial value access address : 000011 h xxxxxxxx b r/w pdrf initial value access address : 000010 h - - - xxxxx b r/w pdrg initial value access address : 000017 h - - xxxxxx b r/w pdrh initial value access address : 000016 h - - xxxxxx b r/w pdri initial value access address : 000015 h - - xxxxxx b r/w pdrj initial value access address : 000014 h - - - - - - 11 b r/w pdrk initial value access address : 00001b h xxxxxxxx b r/w pdrl initial value access address : 00001a h xxxxxxxx b r/w 7654 321 0 p26 p27 p25 p24 p23 p22 p21 p20 7654 321 0 p36 p37 p35 p34 p33 p32 p31 p30 7654 321 0 p46 p47 p45 p44 p43 p42 p41 p40 7654 321 0 p56 p57 p55 p54 p53 p52 p51 p50 7654 321 0 p66 p67 p65 p64 p63 p62 p61 p60 7654 321 0 p86 ? p85 p84 p83 p82 p81 p80 7654 321 0 pc6 pc7 pc5 pc4 pc3 pc2 pc1 pc0 7654 321 0 pd6 pd7 pd5 pd4 pd3 pd2 pd1 pd0 7654 321 0 pe6 pe7 pe5 pe4 pe3 pe2 pe1 pe0 7654 321 0 ? ?? pf4 pf3 pf2 pf1 pf0 7654 321 0 ? ? pg5 pg4 pg3 pg2 pg1 pg0 7654 321 0 ? ? ph5 ph4 ph3 ph2 ph1 ph0 7654 321 0 ? ? pi5 pi4 pi3 pi2 pi1 pi0 7654 321 0 ? ????? pj1 pj0 7654 321 0 pk6 pk7 pk5 pk4 pk3 pk2 pk1 pk0 7654 321 0 pl6 pl7 pl5 pl4 pl3 pl2 pl1 pl0
mb91151a 38 ? data direction register ( ddr ) ddr2 to ddrl control the i/o direction of the i/o port by bit. ddr = 0 : port input ddr = 1 : port output note : ddris bit 6 is a test bit. be sure to write 0 to the bit. 0 is the value that is read. r/w : read/write enabled, w : write only, ? : not in use ddr2 initial value access address : 000601 h 00000000 b w ddr3 initial value access address : 000600 h 00000000 b w ddr4 initial value access address : 000607 h 00000000 b w ddr5 initial value access address : 000606 h 00000000 b w ddr6 initial value access address : 000605 h 00000000 b w ddr8 initial value access address : 00060b h - 0000000 b w ddrc initial value access address : 0000ff h 00000000 b r/w ddrd initial value access address : 0000fe h 00000000 b r/w ddre initial value access address : 0000fd h 00000000 b r/w ddrf initial value access address : 0000fc h - - - 00000 b r/w ddrg initial value access address : 000103 h - - 000000 b r/w ddrh initial value access address : 000102 h - - 000000 b r/w ddri initial value access address : 000101 h - 0000000 b r/w ddrk initial value access address : 000107 h 00000000 b r/w ddrl initial value access address : 000106 h 00000000 b r/w 7654 321 0 p26 p27 p25 p24 p23 p22 p21 p20 7654 321 0 p36 p37 p35 p34 p33 p32 p31 p30 7654 321 0 p46 p47 p45 p44 p43 p42 p41 p40 7654 321 0 p56 p57 p55 p54 p53 p52 p51 p50 7654 321 0 p66 p67 p65 p64 p63 p62 p61 p60 7654 321 0 p86 ? p85 p84 p83 p82 p81 p80 7654 321 0 pc6 pc7 pc5 pc4 pc3 pc2 pc1 pc0 7654 321 0 pd6 pd7 pd5 pd4 pd3 pd2 pd1 pd0 7654 321 0 pe6 pe7 pe5 pe4 pe3 pe2 pe1 pe0 7654 321 0 ? ?? pf4 pf3 pf2 pf1 pf0 7654 321 0 ? ? pg5 pg4 pg3 pg2 pg1 pg0 7654 321 0 ? ? ph5 ph4 ph3 ph2 ph1 ph0 7654 321 0 test ? pi5 pi4 pi3 pi2 pi1 pi0 7654 321 0 pk6 pk7 pk5 pk4 pk3 pk2 pk1 pk0 7654 321 0 pl6 pl7 pl5 pl4 pl3 pl2 pl1 pl0
mb91151a 39 ? pull - up control register ( pcr ) pcr6 to pcri control the pull-up resistor when the corresponding i/o port is in input mode. pcr = 0 : pull-up resistor not available in input mode pcr = 1 : pull-up resistor available in input mode the register has no significance in output mode (a pull-up resistor not available) . pcr6 initial value access address : 000631 h 00000000 b r/w pcrc initial value access address : 0000f7 h 00000000 b r/w pcrd initial value access address : 0000f6 h 00000000 b r/w pcrh initial value access address : 0000f5 h - - 000000 b r/w pcri initial value access address : 0000f4 h - - 000000 b r/w 7654 321 0 p66 p67 p65 p64 p63 p62 p61 p60 7654 321 0 pc6 pc7 pc5 pc4 pc3 pc2 pc1 pc0 7654 321 0 pd6 pd7 pd5 pd4 pd3 pd2 pd1 pd0 7654 321 0 ? ? ph5 ph4 ph3 ph2 ph1 ph0 7654 321 0 ? ? pi5 pi4 pi3 pi2 pi1 pi0 ? open drain control register ( ocr ) ocrh and ocri control open drain when the corresponding i/o port is in output mode. ocr = 0 : standard output port during output mode ocr = 1 : open drain output port during output mode the register has no significance in input mode (output high-z) . ocrh initial value access address : 0000f9 h - - 000000 b r/w ocri initial value access address : 0000f8 h - - 000000 b r/w 7654 321 0 ? ? ph5 ph4 ph3 ph2 ph1 ph0 7654 321 0 ? ? pi5 pi4 pi3 pi2 pi1 pi0 ? analog input control register ( aicr ) the aick controls each pin of a corresponding i/o port as follows : aic = 0 : port input mode aic = 1 : analog input mode the register is reset to 0. r/w : read/write enabled, ? : not in use aick initial value access address : 0000eb h 00000000 b r/w 7654 321 0 pk6 pk7 pk5 pk4 pk3 pk2 pk1 pk0
mb91151a 40 2. dma controller (dmac) the dma controller is a module embedded in fr family devices, and performs dma (direct memory access) transfer. dma transfer performed by the dma controller transfers data without intervention of cpu, contributing to en- hanced performance of the system. ? 8 channels ? mode : single/block transfer, burst transfer and continuous transfer : 3 kinds of transfer ? transfer all through the area ? max 65536 of transfer cycles ? interrupt function right after the transfer ? selectable for address transfer increase/decrease by the software ? external transfer request input pin, external transfer request accept output pin, external transfer complete output pin three pins for each ? block diagram dreq0 to dreq2 edge/level detection circuit data buffer internal resource transfer request dack0 to dack2 deop0 to deop2 interrupt request dpdp switcher sequencer dacsr datcr mode blk dec inc / dec blk dmact sadr dadr 3 3 data bus 3 3 8 5
mb91151a 41 ? registers ( dmac internal registers ) 00000200 h 00000201 h 00000202 h 00000203 h 00000204 h 00000205 h 00000206 h 00000207 h 00000208 h 00000209 h 0000020a h 0000020b h xxxxxxxx b xxxxxxxx b xxxxxxxx b x0000000 b 00000000 b 00000000 b 00000000 b 00000000 b xxxxxxxx b xxxx0000 b xxxx0000 b xxxx0000 b r/w r/w r/w dpdp bit 16 bit 31 address bit 0 initial value dacsr datcr access r/w : read/write enabled x : undefined ? register ( dma descriptor ) bit 31 address bit 0 dpdp + 0 h dpdp + 0c h dpdp + 54 h dma ch0 descriptor dma ch1 descriptor dma ch7 descriptor
mb91151a 42 3. uart the uart is a serial i/o port for asynchronous (start and stop synchronization) communication or clk syn- chronous communication. this product type contains this uart for four channels. its features are as follows : ? full-duplex double buffer ? capable of asynchronous (start and stop synchronization) and clk synchronous communication. ? support for multiprocessor mode ? baud rate by a dedicated baud rate generator ? baud rate by an internal timer the baud rate can be set with a 16-bit reload timer. ? any baud rate can be set using an external clock. ? error detection function (parity, framing, and overrun) ? nrz-encoded transfer signals ? dma transfer can be invoked by interrupt.
mb91151a 43 ? block diagram md1 md0 cs2 cs1 cs0 scke soe pen p sbl cl a / d rec rxe txe pe ore fre rdrf tdre bds rie tie sidr0 to sidr3 internal data bus sodr0 to sodr3 sending start reception error generated signals (to the cpu) (sck0 to sck3) pin receive clock send clock start bit detection circuit receive bit counter receive parity counter receive shift register receiving control circuit sending start circuit send bit counter send parity counter send shift register sending control circuit pin received status determination circuit smr 0 - 3 registers scr 0 - 3 registers ssr 0 - 3 registers clock selector dedicated baud rate generator 16-bit reload timer control bus receive interrupt signal #26 to 29 * send interrupt signal #31 to 34 * (sin0 to sin3) (sot0 to sot3) pin * : interrupt numbers
mb91151a 44 ? register list scr0 scr1 scr2 scr3 smr0 smr1 smr2 smr3 ssr0 ssr1 ssr2 ssr3 sidr0/sodr0 sidr1/sidr1 sidr2/sidr2 sidr3/sidr3 r/w, w r/w, w r/w, w r/w, w r/w r/w r/w r/w r, r/w r, r/w r, r/w r, r/w r, w r, w r, w r, w bit 8 bit 15 address bit 0 initial value 00000100 b 00000100 b 00000100 b 00000100 b 00000-00 b 00000-00 b 00000-00 b 00000-00 b 00001000 b 00001000 b 00001000 b 00001000 b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b 0000001e h 00000022 h 00000026 h 0000002a h 0000001f h 00000023 h 00000027 h 0000002b h 0000001c h 00000020 h 00000024 h 00000028 h 0000001d h 00000021 h 00000025 h 00000029 h access r/w : read/write enabled r : read only w : write only ? : not in use x : undefined
mb91151a 45 4. ppg timer the ppg timer can output highly accurate pwm waveforms efficiently. the mb91151a contains six ppg timer channels and its features are as follows : ? each channel consists of a 16-bit down counter, a 16-bit data register attached with a frequency setting buffer, a 16-bit compare register attached with a duty setting buffer, and a pin controller. ? the count clock for the 16-bit down counter can be selected from the following four types : internal clocks f , f /4, f /16, and f /64 ? the counter value can be initialized by reset or counter borrow to ffff h . ? pwm output (by channel) ? dma transfer can be invoked by interrupt. ? block diagram ( entire configuration ) 4 external trg0 to trg3 external trg4 external trg5 16-bit reload timer channel 0 general control register 1 (factor selection) 16-bit reload timer channel 1 general control register 2 4 pwm0 pwm1 pwm2 pwm3 pwm4 pwm5 trg input pwm timer channel 0 trg input pwm timer channel 1 trg input pwm timer channel 2 trg input pwm timer channel 3 trg input pwm timer channel 4 trg input pwm timer channel 5
mb91151a 46 ? block diagram ( for one channel ) 1 / 1 1 / 4 1 / 16 1 / 64 ck pcsr prescaler peripheral system clock trg input enable ppg mask pwm output inverse bit interrupt selection soft trigger load 16-bit down counter start edge detection borrow pdut cmp s r q irq
mb91151a 47 ? register list (continued) gcn1 gcn2 ptmr0 pcsr0 pdut0 pcnh0 pcnl0 ptmr1 pcsr1 pdut1 pcnh1 pcnl1 ptmr2 pcsr2 pdut2 pcnh2 r/w r/w r w w r/w r/w r w w r/w r/w r w w bit 8 bit 15 address bit 0 initial value 00110010 b 00010000 b 00000000 b 11111111 b 11111111 b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b 0000000- b 00000000 b 11111111 b 11111111 b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b 0000000- b 00000000 b 11111111 b 11111111 b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b 0000000- b 00000094 h 00000095 h 00000097 h 00000098 h 00000099 h 0000009a h 0000009b h 0000009c h 0000009d h 0000009e h 0000009f h 000000a0 h 000000a1 h 000000a2 h 000000a3 h 000000a4 h 000000a5 h 000000a6 h 000000a7 h 000000a8 h 000000a9 h 000000aa h 000000ab h 000000ac h 000000ad h 000000ae h pcnl2 ptmr3 pcsr3 pdut3 pcnh3 pcnl3 r/w r/w r w w r/w r/w 00000000 b 11111111 b 11111111 b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b 0000000- b 00000000 b 000000af h 000000b0 h 000000b1 h 000000b2 h 000000b3 h 000000b4 h 000000b5 h 000000b6 h 000000b7 h accress r/w : read/write enabled r : read only w : write only ? : not in use x : undefined
mb91151a 48 (continued) ptmr4 pcsr4 pdut4 pcnh4 pcnl4 ptmr5 pcsr5 pdut5 pcnh5 pcnl5 r w w r/w r/w r w w r/w r/w 11111111 b 11111111 b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b 0000000- b 00000000 b 11111111 b 11111111 b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b 0000000- b 00000000 b 000000b8 h 000000b9 h 000000ba h 000000bb h 000000bc h 000000bd h 000000be h 000000bf h 000000c0 h 000000c1 h 000000c2 h 000000c3 h 000000c4 h 000000c5 h 000000c6 h 000000c7 h bit 8 bit 15 address bit 0 initial value access r/w : read/write enabled r : read only w : write only ? : not in use x : undefined
mb91151a 49 5. 16-bit reload timer the 16-bit reload timer consists of a 16-bit down counter, a 16-bit reload register, a prescaler for creating internal count clocks, and a control register. the input clock can be selected from three internal clock types (2/8/32 machine clock divisions) . dma transfer can be invoked by interrupt. this product type contains this 16-bit reload timer for four channels. ? block diagram reld oute outl inte uf cnte trg out ctl. csl1 csl0 mod2 mod1 mod0 16 16-bit reload register 16-bit down counter 8 16 2 3 2 clock selector in ctl. f 2 f 2 f 2 1 35 3 exck internal clocks clear prescaler gate retrigger uf reload r bus 2 irq pwm (ch0, ch1) a/d (ch2)
mb91151a 50 ? register lis t tmcsr0 tmcsr1 tmcsr2 tmcsr3 tmr0 tmr1 tmr2 tmr3 tmrlr0 tmrlr1 r/w r/w r/w r/w r r r r w w ----0000 b 00000000 b ----0000 b 00000000 b ----0000 b 00000000 b ----0000 b 00000000 b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b 00000032 h 00000033 h 0000003a h 0000003b h 00000042 h 00000043 h 0000004a h 0000004b h 0000002e h 0000002f h 00000036 h 00000037 h 0000003e h 0000003f h 00000046 h 00000047 h 0000002c h 0000002d h 00000034 h 00000035 h tmrlr2 tmrlr3 w w xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b 0000003c h 0000003d h 00000044 h 00000045 h bit 15 address bit 0 initial value access r/w : read/write enabled r : read only w : write only ? : not in use x : undefined
mb91151a 51 6. bit search module the module searches data written to the input register for 0 or 1 or a change and returns the detected bit position. ? block diagram ? register list d bus address decoder detection mode input latch changing one detection into data bit search circuit search results 000003f0 h 000003f1 h 000003f2 h 000003f3 h 000003f4 h 000003f5 h 000003f6 h 000003f7 h 000003f8 h 000003f9 h 000003fa h 000003fb h xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b w r/w w bsd0 bit 16 bit 31 address bit 0 initial value bsd1 bsdc 000003fc h 000003fd h 000003fe h 000003ff h xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b r bsrr access r/w : read/write enabled r : read only w : write only x : undefined
mb91151a 52 7. 8/10-bit a/d converter (sequential conversion type) the a/d converter is a module that converts analog input voltage into a digital value. its features are as follows : ? a minimum conversion time of 5.0 m s/ch. (including sampling time at a 33 mhz machine clock) ? contains a sample and hold circuit. ? resolution : 10 or 8 bits selectable. ? selection of analog input from eight channels by program ? dma transfer can be invoked by interrupt. ? selection of an invoking factor from software, external pin trigger (falling edge) , and 16-bit reload timer (rising edge) . ? block diagram single conversion mode : selects and converts one channel. continuous conversion mode : converts a specified channel repeatedly. stop and convert mode : stops after converting one channel and stands by until invoked the next time. (conversion invoking can be synchronized.) f mp decoder comparator data register a/d control register 1 a/d control register 2 sample & hold circuit an0 an1 an2 an3 an4 an5 an6 an7 adcr d/a converter sequential compare register input circuit adcs1 , 2 operating clock prescaler 16-bit reload timer 2 external pin trigger av ss avr av ss r - bus
mb91151a 53 ? register list adcr adcs1 adcs0 aick w, r r/w, w r/w r/w 00101-xx b xxxxxxxx b 00000000 b 00000000 b 00000000 b 000000e4 h 000000e5 h 000000e6 h 000000e7 h 000000eb h bit 15 bit 0 initial value access address r r/w : read/write enabled r : read only w : write only ? : not in use x : undefined
mb91151a 54 8. interrupt controller the interrupt controller accepts and arbitrates interrupts. ? block diagram to level0* 4 im nmi processing level determination vector determination level vector generation priority determination int0* 2 or nmi* 6 . . . ri00 ri47 (dlyirq) . . . dlyi* 1 . . icr00 icr47 4 5 5 request to withdraw hldreq 6 r bus 6 level4 hldcan* 3 to vct0* 5 vct5 *1 : dly1 represents the delay interrupt module (delay interrupt generator) . for detailed information, see 10. delay interrupt module. *2 : int0 is a wake-up signal for the clock controller in sleep or stop mode. *3 : hldcan is a bus surrender request signal for bus masters except for the cpu. *4 : level 4 to level 0 are interrupt level outputs. *5 : vct 5 to vct 0 are interrupt vector outputs. *6 : this product type does not have the nmi function.
mb91151a 55 ? register list (continued) icr00 00000400 h r/w ----1111 b icr01 00000401 h r/w ----1111 b icr02 00000402 h r/w ----1111 b icr03 00000403 h r/w ----1111 b icr04 00000404 h r/w ----1111 b icr05 00000405 h r/w ----1111 b icr06 00000406 h r/w ----1111 b icr07 00000407 h r/w ----1111 b icr08 00000408 h r/w ----1111 b icr09 00000409 h r/w ----1111 b icr10 0000040a h r/w ----1111 b icr11 0000040b h r/w ----1111 b icr12 0000040c h r/w ----1111 b icr13 0000040d h r/w ----1111 b icr14 0000040e h r/w ----1111 b icr15 0000040f h r/w ----1111 b icr16 00000410 h r/w ----1111 b icr17 00000411 h r/w ----1111 b icr18 00000412 h r/w ----1111 b icr19 00000413 h r/w ----1111 b icr20 00000414 h r/w ----1111 b icr21 00000415 h r/w ----1111 b icr22 00000416 h r/w ----1111 b icr23 00000417 h r/w ----1111 b icr24 00000418 h r/w ----1111 b icr25 00000419 h r/w ----1111 b icr26 0000041a h r/w ----1111 b icr27 0000041b h r/w ----1111 b icr28 0000041c h r/w ----1111 b icr29 0000041d h r/w ----1111 b icr30 0000041e h r/w ----1111 b icr31 0000041f h r/w ----1111 b icr32 00000420 h r/w ----1111 b icr33 00000421 h r/w ----1111 b icr34 00000422 h r/w ----1111 b icr35 00000423 h r/w ----1111 b icr36 00000424 h r/w ----1111 b icr37 00000425 h r/w ----1111 b icr38 00000426 h r/w ----1111 b icr39 00000427 h r/w ----1111 b bit 7 bit 0 bit 7 bit 0 address initial value address initial value access access r/w : read/write enabled ? : not in use
mb91151a 56 (continued) icr40 00000428 h r/w ----1111 b icr41 00000429 h r/w ----1111 b icr42 0000042a h r/w ----1111 b icr43 0000042b h r/w ----1111 b icr44 0000042c h r/w ----1111 b icr45 0000042d h r/w ----1111 b icr46 0000042e h r/w ----1111 b icr47 0000042f h r/w ----1111 b hrcl 00000431 h r/w ----1111 b dicr 00000430 h r/w -------0 b bit 7 bit 0 address initial value access r/w : read/write enabled ? : not in use
mb91151a 57 9. external interrupt the external interrupt controller controls external interrupt requests input to int0 through int15. the level of requests to be detected can be selected from h, l, rising edge, and falling edge. ? block diagram ? register list 10. delay interrupt module the delay interrupt is a module that generates task switching interrupts. the use of this module allows the software to generate/cancel interrupt requests to the cpu. for the block diagram of the delay interrupt module, see 8. interrupt controller. ? register list 16 interrupt permission register interrupt factor register request level setting register r bus 16 32 16 interrupt request gate factor f/f edge detection circuit 16 int0 to int15 eirr0 eirr1 enir0 enir1 elvr0 elvr1 r/w r/w r/w r/w 00000000 b 00000000 b 00000000 b 00000000 b 00000000 b 00000000 b 00000000 b 00000000 b 000000c8 h 000000c9 h 000000ca h 000000cb h 000000cc h 000000cd h 000000ce h 000000cf h bit 8 bit 15 address bit 0 initial value access r/w : read/write enabled dicr r/w bit 7 address bit 0 initial value -------0 b 00000430 h access r/w : read/write enabled ? : not in use
mb91151a 58 11. clock generator (low power consumption mechanism) the clock generator is responsible for the following functions : ? cpu clock generation (including the gear function) ? peripheral clock generation (including the gear function) ? reset generation and holding factors ? standby function (including hardware standby) ? contains pll (multiplication circuit) ? block diagram x0 [gear controller] [stop/sleep controller] [reset factor circuit] [watchdog controller] gcr register cpu gear cpu clock internal bus clock stop state sleep state cpu hold request internal reset internal peripheral clock peripheral gear internal clock generating circuit status transition control circuit oscillator circuit x1 v cc power on detection circuit gnd rsrr register wpr register timebase timer ctbr register watchdog f/f count clock rst pin m p x pll reset generating f/f stcr register pdrr register internal interrupt internal reset dma request 1 / 2 r
mb91151a 59 ? register list rsrr / wtcr stcr pdrr ctbr gcr wpr r/w, w w r/w, r w bit 8 bit 15 bit 0 000111-- b r, w 1-xxx-00 b r/w ----0000 b xxxxxxxx b 110011-1 b xxxxxxxx b 00000481 h 00000482 h 00000483 h 00000480 h 00000484 h 00000485 h address initial value access r/w : read/write enabled r : read only w : write only ? : not in use x : undefined
mb91151a 60 12. external bus interface the external bus interface controls the interface between the external memory and the external i/o. its features are as follows : ? 24-bit (16 mb) address output ? an 8/16-bit bus width can be set by chip select area. ? inserts an automatic and programmable memory wait (for seven cycles at maximum) . ? unused addresses/data pins are available as i/o ports. ? support for little endian mode ? when use of a clock doubler, bus speed is half of cpu. ? the use is not allowed when the external bus exceeds 25 mhz. ? block diagram write buffer read buffer address buffer switch switch a-out m u x external data bus asr amr registers & control external pin controller 3 4 4 shifter comparator controls all blocks. inpage + 1 or + 2 data block address block external address bus cs0 to cs3 rd wr0, wr1 brq bgrnt rdy clk address bus data bus
mb91151a 61 ? register list asr1 amr1 asr2 amr2 asr3 amr3 asr4 amr4 asr5 amr5 amd0 amd1 amd32 amd4 amd5 epcr0 w w r/w r/w r/w r/w r/w bit 16 bit 31 bit 0 00000000 b 00000001 b 00000000 b 00000010 b w 00000000 b 00000000 b w 00000000 b 00000011 b w 00000000 b 00000000 b w w 00000000 b 00000100 b w 00000000 b 00000000 b 00000000 b 00000000 b w 00000000 b 00000000 b w 00000000 b 00000101 b w -------- b 11111111 b w ----1100 b -1111111 b ---00111 b 0--00000 b 00000000 b 0--00000 b 0--00000 b 0000060c h 0000060d h 0000060e h 0000060f h 00000610 h 00000611 h 00000612 h 00000613 h 00000614 h 00000615 h 00000616 h 00000617 h 00000618 h 00000619 h 0000061a h 0000061b h 0000061c h 0000061d h 0000061e h 0000061f h 00000628 h 00000629 h 0000062a h 0000062b h 00000620 h 00000621 h 00000622 h 00000623 h 00000624 h 000007fe h epcr1 ler modr w w -----000 b xxxxxxxx b 000007ff h address initial value access r/w : read/write enabled w : write only ? : not in use x : undefined
mb91151a 62 13. multifunction timer the multifunction timer unit consists of one 16-bit free-run timer, eight 16-bit output compare registers, four 16- bit input capture registers, and six 16-bit ppg timer channels. by using this function waveforms can be output based on the 16-bit free-run timer and the input pulse width and external clock cycle can also be measured. ?timer components ? 16-bit free-run timer ( 1) the 16-bit free-run timer consists of a 16-bit up counter, a control register, a 16-bit compare clear register, and a prescaler. the output value of this counter is used as the basic time (base timer) for output compare and input capture. ? output compare ( 8) the output compare consists of eight 16-bit compare registers, a compare output latch, and a control register. when the 16-bit free-run timer value agrees to the compare register value, the output level can be inverted and an interrupt can also be generated. ? input capture ( 4) the input capture consists of capture registers corresponding to four independent external input pins and a control register. by detecting any edge of signals input from external input pins, the 16-bit free-run timer value can be held in the capture register and an interrupt can be generated at the same time. ? 16-bit ppg timer ( 6) see 4. ppg timer.
mb91151a 63 ? block diagram f ivf r-bus ivfe stop interrupt interrupt interrupt interrupt interrupt interrupt 16-bit free-run timer compare register 0/2/4/6 compare circuit compare register 1/3/5/7 compare circuit capture register 0/2 capture register 1/3 16-bit compare clear register (channel 6's compare register) mode sclr clk2 clk1 clk0 divider compare circuit clock iclr iop1 iop0 ioe1 ioe0 icp0 icp1 ice0 ice1 eg11 eg10 eg01 eg00 in 0/2 in 1/3 cmod select oc0/2/4/6 tq oc1/3/5/7 t edge detection edge detection q icre ms13 to 0
mb91151a 64 ? register list bit15 bit8 bit7 bit0 ipcp1 ipcp0 ipcp3 ipcp2 occp1 occp0 occp3 occp2 occp5 occp4 occp7 occp6 ocs3,2 ocs1,0 ocs7,6 ocs5,4 tcdt tccs ics23 ics01 000068 h 000069 h 00006a h 00006b h 00006c h 00006d h 00006e h 00006f h 000071 h 000073 h 000074 h 000075 h 000076 h 000077 h 000078 h 000079 h 00007a h 00007b h 00007c h 00007d h 00007e h 00007f h 000080 h 000081 h 000082 h 000083 h 000084 h 000085 h 000086 h 000087 h 000088 h 000089 h 00008a h 00008b h 00008c h 00008d h 00008e h 00008f h xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b 00000000 b 00000000 b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxx00000 b 0000xx00 b xxx00000 b 0000xx00 b xxx00000 b 0000xx00 b xxx00000 b 0000xx00 b 00000000 b 00000000 b 0 - - - - - - - b 00000000 b address initial value access r r r r r r r r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w : read/write enabled r : read only ? : not in use x : undefined
mb91151a 65 14. 8-bit d/a converter this block is of an 8-bit resolution, r-2r d/a converter. the block contains three d/a converter channels and each d/a control register can control output independently. the d/a converter pin is a dedicated pin. ? block diagram da27 da27 ~ da20 da17 ~ da10 da07 ~ da00 davc da20 dae2 dae1 dae0 da17 davc da10 da07 davc da00 r - bus standby control standby control standby control d/a output channel 2 d/a output channel 1 d/a output channel 0
mb91151a 66 ? register list r/w : read/write enabled, ? : not in use, x : undefined initial value access address : 00000e3 h xxxxxxxx b r/w initial value address : 00000e2 h xxxxxxxx b r/w initial value address : 00000e1 h xxxxxxxx b r/w initial value address : 00000df h - - - - - - - 0 b r/w initial value address : 00000de h - - - - - - - 0 b r/w initial value address : 00000dd h - - - - - - - 0 b r/w bit 7 654 3 21 0 dadr0 bit 15 14 13 12 11 10 9 8 dadr1 bit 23 22 21 20 19 18 17 16 dadr2 bit 7 654 3 21 0 dacr0 bit 15 14 13 12 11 10 9 8 dacr1 bit 23 22 21 20 19 18 17 16 dacr2
mb91151a 67 15. 8/16-bit up/down counters/timers this is the up/down counter/timer block consisting of six event input pins, two 8-bit up/down counters, two 8-bit reload/compare registers, and their control circuits. the features of this module are as follows : ? capable of counting in the (0) d- (255) d range by the 8-bit count register. (in 16-bit 1 operating mode, the register can count in the (0) d- (65535) d range.) ? four count modes to choose from by the count clock. ? in timer mode the count clock can be selected from two internal clock types. ? in up/down count mode an external pin input signal detection edge can be selected. ? the phase-difference count mode is suitable for encoder counting, such as of motors. rotation angles, rotating speeds, and so on can be counted accurately and easily by inputting the output of phases a, b, and z. ? two types of function to choose from for the zin pin. (enabled in all modes) ? equipped with compare and reload functions which can be used individually or in combination. when combined, these functions can count up/down at any width. ? the immediately preceding count direction can be identified by the count direction flag. ? capable of individually controlling interrupt generation when comparison results match, at occurrence of reload (underflow) or overflow, or when the count direction changes.
mb91151a 68 ? block diagram zin0 cge1 udcc ucre counter clear rlde carry cmpf ovff udff udie cite counter clock interrupt output udf1 cstr bin0 prescaler ain0 clks ces1 up/down count clock selection ces0 cms1 cms0 udf0 cdcf cfie rcut reload control edge/level detection 8 bit rcr0 (reload/compare register 0) udcr0 (up/down count register 0) data bus 8 bit cge0 c/gs ? 8/16-bit up/down counter/timer (channel 0)
mb91151a 69 zin1 cge1 udcc ucre rlde carry counter clock interrupt output cmpf ovff udff udie cite udf1 cstr bin1 ain1 clks prescaler ces1 ces0 m16e cms1 up/down count clock selection cms0 udf0 cdcf cfie rcut counter clear reload control edge/level detection 8 bit data bus rcr1 (reload/compare register 1) udcr1 (up/down count register 1) 8 bit cge0 c/gs ? 8/16-bit up/down counter/timer (channel 1)
mb91151a 70 ? register list r/w : read/write enabled, r : read only, w : write only, ? : not in use, x : undefined initial value access address : 00005f h 00000000 b r initial value address : 00005e h 00000000 b r initial value address : 00005d h 00000000 b w initial value address : 00005c h 00000000 b w initial value address : 000063 h 00000000 b r/w, r initial value address : 000067 h 00000000 b r/w, r initial value address : 000061 h -000x000 b r/w, w initial value address : 000065 h -000x000 b r/w, w initial value address : 000060 h 00000000 b r/w initial value address : 000064 h -0000000 b r/w bit 7 654 3 21 0 udcr0 bit 15 14 13 12 11 10 9 8 udcr1 bit 7 654 3 21 0 rcr0 bit 15 14 13 12 11 10 9 8 rcr1 bit 7 654 3 21 0 csr0 bit 7 654 3 21 0 csr1 bit 7 654 3 21 0 ccrl0 bit 7 654 3 21 0 ccrl1 bit 15 14 13 12 11 10 9 8 ccrh0 bit 15 14 13 12 11 10 9 8 ccrh1
mb91151a 71 16. peripheral stop control this function can be used to stop the clock of unused resources in order to conserve more power. ? register list bit7 bit0 stpr0 000090 h 0000 - - - - b stpr1 000091 h 00000 - 00 b stpr2 000092 h 000000 - - b address initial value access r/w r/w r/w r/w : read/write enabled, ? : not in use
mb91151a 72 n serial start up the serial startup mode is the internal ram (2 kb) serial write or ram program startup mode using the internal dedicated rom. while this mode executes communication through the uart channel 1 built in this model, it can also serve for data transfer to external flash memory. either synchronous or asynchronous communication can be selected by setting the relevant pin. for asynchronous communication, a baud rate of 9600 bps can be used either at a machine clock frequency of 25 mhz (oscillation frequency of 12.5 mhz) orat a machine clock frequency of 33 mhz (oscillation frequency of 16.5 mhz) selectively. (note that serial startup using asynchronous communication cannot be performed at a machine clock frequency of 36 mhz at an oscillation frequency of 18 mhz.) ? communication specifications (1) asynchronous communication at a machine clock frequency of 33 mhz the device performs serial communication in the asynchronous (normal) mode of uart channel 1. the baud rate is 9600 bps at a machine clock frequency of 33 mhz (based on a 16.5 mhz external crystal oscillator) . serial mode settings are : a data length of 8 bits, a stop bit length of 1 bit, no parity, and lsb-first transfer. (2) asynchronous communication at a machine clock frequency of 25 mhz the device performs serial communication in the asynchronous (normal) mode of uart channel 1. the baud rate is 9600 bps at a machine clock frequency of 25 mhz (based on a 12.5 mhz external crystal oscillator) . serial mode settings are : a data length of 8 bits, a stop bit length of 1 bit, no parity, and lsb-first transfer. (3) synchronous communication the device performs serial communication in the synchronous (normal) mode of uart channel 1. the baud rate can be set freely depending on the external clock input (the baud rate is determined directly by the external clock frequency) . the maximum input frequency of the external clock is the peripheral operating clock frequency devided by 8. (the peripheral operating clock setting is the fastest pll frequency.) serial mode settings are : a data length of 8 bits, no parity, and lsb-first transfer. in each fo these modes, the devices passes the following three items of download information data to the fr, byte by byte in sequence from the high-order byte : 1. command data (00 h ) 2. 4 bytes of the download destination ram address (00080400 h to 000807ff h ) 3. 4 bytes specifying the number of bytes download (up to 000003ff h ) then the device gives resulting sum check data (the lower eight bits extracted from these data items added together) , entering the ram download routine. the device then passes the data to be downloaded to ram to the fr, byte by byte in sequence from the high- order byte, and the resulting sum check data as well in the same way. upon completion of transfer, a jump to ram takes place and the downloaded program is executed. method of setting external pin name md2 md1 md0 pg5 pg4 pg3 asynchronous communication machine clock 33 mhz 110100 asynchronous communication machine clock 25 mhz 110101 synchronous communication 1 1 0 1 1 0
mb91151a 73 n electrical characteristics 1. absolute maximum ratings (v ss = av ss = 0.0 v) *1 : take care not to exceed v cc + 0.3 v when turning on the power, for example. take care also to prevent av cc from exceeding v cc when turning on the power, for example. *2 : the maximum output current stipulates the peak value of a single concerned pin. *3 : the average output current stipulates the average current flowing through a single concerned pin over a period of 100 ms. *4 : the total average output current stipulates the average current flowing through all concerned pins over a period of 100 ms. warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. parameter symbol rating unit remarks min max power supply voltage v cc v ss - 0.3 v ss + 3.6 v analog supply voltage av cc v ss - 0.3 v ss + 3.6 v *1 analog reference voltage avrh v ss - 0.3 v ss + 3.6 v *1 input voltage v i v ss - 0.3 v cc + 0.3 v input voltage (open drain port j) v i2 v ss - 0.3 v ss + 5.5 v analog pin input voltage v ia v ss - 0.3 av cc + 0.3 v output voltage v o v ss - 0.3 v cc + 0.3 v l level maximum output current i ol ? 10 ma *2 l level average output current i olav ? 4ma*3 l level total maximum output current s i ol ? 100 ma l level total average output current s i olav ? 50 ma *4 h level maximum output current i oh ?- 10 ma *2 h level average output current i ohav ?- 4ma*3 h level total maximum output current s i oh ?- 50 ma h level total average output current s i ohav ?- 20 ma *4 power consumption p d ? 500 mw operating temperature t a 0 + 70 c storage temperature tstg - 55 + 150 c
mb91151a 74 2. recommended operating conditions (v ss = av ss = 0.0 v) warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the devices electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol value unit remarks min max power supply voltage v cc 3.15 3.6 v during normal operations. 2.0 3.6 the ram state is retained when stopped. analog supply voltage av cc v ss + 3.15 v ss + 3.6 v analog reference voltage (high voltage side) avrh av cc - 0.3 av cc v analog reference voltage (low voltage side) avrl av ss av ss + 0.3 v operating temperature t a 0 + 70 c
mb91151a 75 3. dc characteristics (v cc = 3.15 v to 3.6 v, v ss = av ss = 0 v, t a = 0 c to + 70 c) * : see n i/o circuit type. parameter symbol pin name condition value unit remarks min typ max h level input voltage v ih input except for hysteresis input pin* ? 0.65 v cc ? v cc + 0.3 v v ihs hysteresis input pin* ? 0.8 v cc ? v cc + 0.3 v l level input voltage v il input except for hysteresis input pin* ? v ss - 0.3 ? 0.25 v cc v v ils hysteresis input pin* ? v ss - 0.3 ? 0.2 v cc v h level output voltage v oh except for port j. v cc = 3.15 v, i oh = 4.0 ma v cc - 0.5 ?? v l level output voltage v ol except for port j. v cc = 3.15 v, i ol = 4.0 ma ? 0.4 v input leakage current i li ? v cc = 3.6 v, v ss mb91151a 76 4. ac characteristics (1) clock timing ratings (v cc = 3.15 v to 3.6 v, v ss = av ss = 0 v, t a = 0 c to + 70 c) *1 : the target analog section is the a/d. *2 : the maximum external bus operating frequency allowed is 25 mhz. *3 : the value when a minimum clock frequency of 10 mhz is input to x0 and half a division of the oscillator circuit and the 1/8 gear are in use. parameter sym- bol pin name condition value unit remarks min max clock frequency (high speed and self oscilla- tion) f c x0, x1 ? 10 18 mhz range in which self oscillation is allowed clock frequency (high speed and pll in use) ? range in which self oscillation and the use of the pll for ex- ternal clock input are allowed clock frequency (high speed an 1/2 division input) ? 10 18 mhz range in which exter- nal clocks can be in- put clock cycle time t c x0, x1 ? 55.6 100 ns input clock pulse width p wh x0, x1 ? 25 ? ns p wl 15 ? ns input clock rising t cr x0, x1 ?? 8ns (t cr + t cf ) input clock falling t cf internal operat- ing clock fre- quency cpu system f cp ? one wait is set with the wait con- troller. 0.625* 3 36 mhz bus system f cpb 0.625* 3 25* 2 peripheral system f cpp 0.625* 3 33 analog section ex- cluded. * 1 1 33 analog section * 1 internal operat- ing clock cycle time cpu system t cp ? 27.8 1600* 3 ns bus system t cpb 40* 2 1600* 3 peripheral system t cpp 30.3 1600* 3 analog section ex- cluded. * 1 30.3 1000 analog section * 1
mb91151a 77 the relationship between the x0 input and the internal clock set with the chc/cck1/cck0 bit of the gcr (gear control register) is as shown next. t c t cf t cr p wh p wl v cc 3.6 3.15 f cpp f cp 0.625 m operation assurance range frequency (hz) supply voltage (v) 36 m t cyc t cyc t cyc t cyc t cyc t cyc t cyc t cyc x0 input ? source oscillation 1 (gcr chc bit : 0) (a) gear 1 internal clock cck1/0 : 00 (b) gear 1/2 internal clock cck1/0 : 01 (c) gear 1/4 internal clock cck1/0 : 10 (d) gear 1/8 internal clock cck1/0 : 11 ? source oscillation 1/2 (gcr chc bit : 1) (a) gear 1 internal clock cck1/0 : 00 (b) gear 1/2 internal clock cck1/0 : 01 (c) gear 1/4 internal clock cck1/0 : 10 (d) gear 1/8 internal clock cck1/0 : 11
mb91151a 78 (2) clock output timing (v cc = 3.15 v to 3.6 v, v ss = av ss = 0 v, t a = 0 c to + 70 c) *1 : t cyc is a frequency for one clock including a gear cycle. the doubler is used when the cpu runs at 25 mhz or higher. *2 : rating at a gear cycle of 1. when a gear cycle of 1/2, 1/4, or 1/8 is set, substitute 1/2, 1/4, or 1/8 for n in the following equations, respectively. min : (1 - n/2) t cyc - 10 max : (1 - n/2) t cyc + 10 when the doubler is used, set the gear cycle to 1. *3 : rating at a gear cycle of 1. when a gear cycle of 1/2, 1/4, or 1/8 is set, substitute 1/2, 1/4, or 1/8 for n in the following equations, respectively. min : n/2 t cyc - 10 max : n/2 t cyc + 10 when the doubler is used, set the gear cycle to 1. parameter symbol pin name condition value unit remarks min max cycle time t cyc clk ? t cp ? ns *1 t cpb ? at using doubla clk -? clk t chcl clk t cyc /2 - 10 t cyc /2 + 10 ns *2 clk ? clk - t clch clk t cyc /2 - 10 t cyc /2 + 10 ns *3 clk t clch t chcl t cyc voh vol voh
mb91151a 79 (3) reset input ratings (v cc = 3.15 v to 3.6 v, v ss = av ss = 0 v, t a = 0 c to + 70 c) (4) power on reset (v cc = 3.15 v to 3.6 v, v ss = av ss = 0 v, t a = 0 c to + 70 c) parameter symbol pin name condition value unit remarks min max reset input time t rstl rst ? t cp 5 ? ns parameter symbol pin name condition value unit remarks min max power supply rising time t r v cc ? ? 20 ms v cc < 0.2 v before turning up the power. power supply cutoff time t off 2 ? ms rst t rstl 0.2 v cc v cc t r 0.9 v cc 0.2 v holding ram data. t off v cc v ss v cc rst t rstl a rapid change in supply voltage might activate power on reset. when the supply voltage needs to be varied while operating, it is recommended to minimize fluctuations to smoothly start up the voltage. it is recommended to keep the rising inclination less than 50 mv/ms. when turning on the power, start the rst pin in l level state, allow as much time as for t rstl after reaching the v cc power supply level and then set the pin to the h level.
mb91151a 80 (5) serial i/o (ch0 to ch4) (v cc = 3.15 v to 3.6 v, v ss = av ss = 0 v, t a = 0 c to + 70 c) parameter symbol pin name condition value unit remarks min max serial clock cycle time t scyc ? internal clock 8 t cpp ? ns sck ? sot delay time t slov ?- 10 + 50 ns valid sin ? sck - t ivsh ? 50 ? ns sck - ? valid sin hold time t shix ? 50 ? ns serial clock h pulse width t shsl ? external clock 4 t cpp - 10 ? ns serial clock l pulse width t slsh ? 4 t cpp - 10 ? ns sck ? sot delay time t slov ? 050ns valid sin ? sck - t ivsh ? 50 ? ns sck - ? valid sin hold time t shix ? 50 ? ns serial busy period t busy ?? 6 t cpp ns sck sot sin t shix t ivsh t slov t scyc sck sot sin t busy t ivsh t shix t slov t slsh t shsl internal shift clock mode external shift clock mode
mb91151a 81 (6) external bus measurement conditions the following conditions apply to items that are not specifically stipulated. ? ac characteristics measurement conditions v cc : 3.3 v ? load condition v ih input output v il v oh v ol v cc 0 v (the input rise/fall time is less than 10 ns.) v ih 2.4 v v oh 1/2v cc v il 0.8 v v ol 1/2v cc c = 50 pf ( v cc : 3.3 v ) output pin
mb91151a 82 (7) normal bus access and read/write operations (v cc = 3.15 v to 3.6 v, v ss = av ss = 0 v, t a = 0 c to + 70 c) *1 : if the bus is extended with either automatic wait insertion or rdy input, add the (t cyc the number of extended cycles) time to this value. *2 : this is the value at the time of (gear cycle 1) . when the gear cycle is set to 1/2, 1/4 or 1/8, substitute n in the following formula with 1/2, 1/4 or 1/8 respectively. formula : (2 - n / 2) t cyc - 13 parameter symbol pin name condition value unit remarks min max cs0 to cs3 delay time t chcsl clk cs0 to cs3 ? ? 15 ns cs0 to cs3 delay time t chcsh ? 15 ns address delay time t chav clk a23 to a00 ? 15 ns data delay time t chdv clk d31 to d16 ? 15 ns rd delay time t clrl clk rd ? 10 ns rd delay time t clrh ? 10 ns wr0 to wr1 delay time t clwl clk wr0 to wr1 ? 10 ns wr0 to wr1 delay time t clwh ? 10 ns valid address ? valid data input time t avdv a23 to a00 d31 to d16 ? 3 / 2 t cyc - 13 ns *1, *2 rd ? valid data input time t rldv rd d31 to d16 ? t cyc - 25 ns *1 data setup ? rd - time t dsrh 25 ? ns rd - ? rdata hold time t rhdx 0 ? ns
mb91151a 83 t cyc t chcsh t chcsl t chav t clrl t clrh t rldv t avdv t rhdx ba1 ba2 v oh v ol v oh v oh v oh v ol v ol v oh v ol v ol v il v ih read v il v ih v oh t dsrh v oh v ol v oh write v ol t clwh t clwl t chdv clk cs0 to cs3 a23 to a00 rd d31 to d16 wr0 to wr1 d31 to d16
mb91151a 84 (8) ready input timing (v cc = 3.15 v to 3.6 v, v ss = av ss = 0 v, t a = 0 c to + 70 c) parameter symbol pin name condition value unit remarks min max rdy setup time ? clk t rdys rdy clk ? 20 ? ns clk ? rdy hold time t rdyh rdy clk 0 ? ns clk when rdy wait is applied when rdy wait is not applied v il v ih v ih v il v il v oh v oh v ol v ol v ih v ih v il t rdyh t rdys t rdyh t rdys t cyc
mb91151a 85 (9) hold timing (v cc = 3.15 v to 3.6 v, v ss = av ss = 0 v, t a = 0 c to + 70 c) note : more than one cycle exist after brq is fetched and before bgrnt changes. parameter symbol pin name condition value unit remarks min max bgrnt delay time t chbgl clk bgrnt ? ? 10 ns bgrnt delay time t chbgh ? 10 ns pin floating ? bgrnt time t xhal bgrnt t cyc - 10 t cyc + 10 ns bgrnt - ? pin valid time t hahv t cyc - 10 t cyc + 10 ns clk v oh v oh v ol high impedance v oh t chbgl t xhal t hahv t chbgh tcyc v oh brq bgrnt each pin
mb91151a 86 (10) dma controller timing (v cc = 3.15 v to 3.6 v, v ss = av ss = 0 v, t a = 0 c to + 70 c) parameter symbol pin name condition value unit remarks min max dreq input pulse width t drwh dreq0 to dreq2 ? 2 t cyc ? ns dack delay time (typical bus) (typical dram) t cldl clk dack0 to dack2 ? 6ns t cldh ? 6ns deop delay time (typical bus) (typical dram) t clel clk deop0 to deop2 ? 6ns t cleh ? 6ns dack delay time (single dram) (hyper dram) t chdl clk dack0 to dack2 ? n / 2 t cyc ns t chdh ? 6ns deop delay time (single dram) (hyper dram) t chel clk deop0 to deop2 ? n / 2 t cyc ns t cheh ? 6ns clk v ol v ol v oh v oh v ih v ih t clel t cldl t cleh t cldh t chdh t chdl t chel t drwh v oh v ol v ol v oh tcyc dack0 to dack2 deop0 to deop2 dack0 to dack2 deop0 to deop2 dreq0 to dreq2 ( single dram ) ( hyper dram ) (typical bus) (typical dram)
mb91151a 87 5. a/d converter electrical characteristics (v cc = 3.15 v to 3.6 v, v ss = av ss = 0 v, t a = 0 c to + 70 c) notes : the smaller the |avrh| is, the greater the error is in general. the external circuit output impedance of analog input should be used in compliance with the following requirements : external circuit output impedance 2 (k w ) if the output impedance of the external circuit is too high, an analog voltage sampling duration shortage might occur. (sampling duration = 1.4 m s : @33 mhz) parameter sym- bol pin name condition value unit re- marks min typ max resolution ?? ? ?? 10 bit conversion time ?? 5.1 ??m s total error ?? av cc = 3.3 v, avrh = 3.3 v ?? 4.0 lsb linearity error ?? ? ? 3.5 lsb differential linearity error ?? ? ? 2.0 lsb zero transition error v ot an0 to an7 av cc = 3.3 v, av rh = 3.3 v av ss - 1.5 av ss + 0.5 av ss + 2.5 lsb full-scale transition error v fst an0 to an7 av rh - 5.5 av rh - 1.5 av rh + 0.5 lsb analog input current i ain an0 to an7 ? ? 0.1 10 m a analog input voltage v ain an0 to an7 av ss ? av rh v reference voltage av rh avrh ??? av cc v supply cur- rent conversion in operation i a av cc av cc = 3.3 v ? 3.0 5.0 ma conversion stopped i ah ?? 5.0 m a reference voltage supply cur- rent conversion in operation i r avrh av cc = 3.3 v, avrh = 3.3 v ? 2.0 3.0 ma conversion stopped i rh ?? 10 m a interchannel variation ? an0 to an7 ??? 4lsb
mb91151a 88 ? a / d converter glossary (continued) ? resolution : analog changes that are identifiable by the a/d converter. ? linearity error : the deviation of the straight line connecting the zero transition point (00 0000 0000 ?? 00 0000 0001) with the full-scale transition point (11 1111 1110 ?? 11 1111 1111) from actual conversion characteristics. ? differential linearity error : the deviation of input voltage needed to change the output code by one lsb from the theoretical value. ? total error : the difference between actual and theoretical conversion values including a zero transition/full-scale transition/linearity error. 3ff 3fe 3fd 004 003 002 001 av ss avrh analog input 0.5 lsb' { 1 lsb' ( n - 1 ) + 0.5 lsb' } 1.5 lsb' theoretical characteristics actual conversion characteristics v nt (actual measurement) actual conversion characteristics total error digital output total error of digital output n = v nt - {1 lsb (n - 1) + 0.5 lsb} 1 lsb 1 lsb (theoretical value) = avrh - av ss 1024 [v] v ot (theoretical value) = v nt : voltage at which digital output changes from (n + 1) to n. av ss + 0.5 lsb [v] v fst (theoretical value) = avrh - 1.5 lsb [v]
mb91151a 89 (continued) 6. d/a converter electrical characteristics (v cc = 3.15 v to 3.6 v, v ss = av ss = 0 v, t a = 0 c to + 70 c) * : cl = 20 pf parameter symbol pin name condi- tion value unit re- marks min typ max resolution ?? ? ? ? 8bit differential linearity error ?? ? ? ? 1lsb conversion time ?? ? ? ? 20 m s* analog output impedance ?? ? ? 29 ? k w linearity error of digital output n = v nt - {1 lsb (n - 1) + v ot } 1 lsb [lsb] differential linearity error of digital output n = v ( n + 1 ) t - v nt 1 lsb - 1 1 lsb = v fst - v ot 1022 [v] v ot : voltage at which digital output changes from (000) h to (001) h . v fst : voltage at which digital output changes from (3fe) h to (3ff) h . [lsb] 3ff 3fe 3fd 004 003 002 001 av ss avrh analog input theoretical characteristics actual conversion characteristics digital output actual conversion characteristics linearity error { 1 lsb ( n - 1 ) + v ot } v fst (actual measurement) v nt (actual measurement) v ot (actual measurement) n + 1 n n - 1 n - 2 av ss avrh analog input actual conversion characteristics actual conversion characteristics theoretical characteristics digital output differential linearity error v fst (actual measurement) v nt (actual measurement)
mb91151a 90 n example characteristics (continued) (1) h level output voltage (2) l level output voltage h output voltage vs. power supply voltage l output voltage vs. power supply voltage (3) l level output voltage (open drain) (4) pull-up resistance l output voltage (open drain) vs. power supply voltage pull-up resistance vs. power supply voltage 5 4 3 2 1 0 2.8 4.2 3.8 3.6 3.4 3.0 v cc [v] voh [v] 3.2 4.0 400 300 250 150 100 0 2.8 4.2 3.8 3.6 3.4 3.0 v cc [v] vol [mv] 3.2 4.0 350 200 50 400 300 250 150 100 0 2.8 4.2 3.8 3.6 3.4 3.0 v cc [v] vol [mv] 3.2 4.0 350 200 50 80 60 50 30 20 0 2.8 4.2 3.8 3.6 3.4 3.0 v cc [v] r [k ] 3.2 4.0 70 40 10
mb91151a 91 (continued) (5) power supply current (6) power supply current at sleeping power supply current vs. voltage power supply current (sleep) vs. voltage (7) power supply current at stopping (8) a/d conversion power supply voltage (36 mhz) power supply current (stop) vs. voltage a/d conversion power supply voltage vs. power supply voltage (9) a/d conversion reference power supply current (36 mhz) (10) d/a conversion reference power supply current per 1 ch a/d conversion reference power supply current vs. voltage d/a conversion reference power supply current per 1 ch vs. power supply voltage 120 100 80 60 40 0 2.8 3.8 3.6 3.4 3.0 v cc [v] icc [ma] 3.2 20 100 80 60 40 0 iccs [ma] 20 2.8 3.8 3.6 3.4 3.0 v cc [v] 3.2 90 70 50 30 10 120 80 60 40 0 icch [ a] 2.8 3.8 3.6 3.4 3.0 v cc [v] 3.2 100 20 5 4 3 2 0 ia [ma] 1 2.8 3.8 3.6 3.4 3.0 v cc [v] 3.2 2.0 1.5 1.0 0.5 0.0 ir [ma] 2.8 3.8 3.6 3.4 3.0 v cc [v] 3.2 1.0 0.8 0.6 0.4 0.0 iada [ma] 0.2 2.8 3.8 3.6 3.4 3.0 v cc [v] 3.2
mb91151a 92 n ordering information part number package remarks MB91151APMT2-G 144-pin plastic lqfp (fpt-144p-m08)
mb91151a 93 n package dimension 144-pin plastic lqfp (fpt-144p-m08) *pins width and pins thickness include plating thickness. dimensions in mm (inches) c 2000 fujitsu limited f144019s-c-2-4 details of "a" part 0.25(.010) (stand off) (.004?004) 0.10?.10 (.024?006) 0.60?.15 (.020?008) 0.50?.20 1.50 +0.20 ?.10 +.008 ?004 .059 0?8 0.50(.020) "a" 0.08(.003) 0.145?.055 (.006?002) lead no. 1 36 index 37 72 73 108 109 144 0.22?.05 (.009?002) m 0.08(.003) 20.00?.10(.787?004)sq 22.00?.20(.866?008)sq (mounting height)
mb91151a fujitsu limited all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). please note that fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan. f 0206 ? fujitsu limited printed in japan

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